公开(公告)号：US4468735A

公开(公告)日：1984-08-28

申请号：US378959

申请日：1982-05-17

申请人： Volkmar Gotze ,  Gunther Potz

发明人： Volkmar Gotze ,  Gunther Potz

IPC分类号： H03K19/177 ,  G06F7/00

CPC分类号： H03K19/17712

摘要： A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.

摘要翻译： 可编程逻辑阵列（PLA）由通常以AND和OR阵列布置的双重个性化单元组成。 为了激活冗余或不关心位置，即不用于执行各个PLA功能的阵列位置，在AND阵列之前以及在AND和OR阵列之间提供控制电路。 这允许由给定的PLA增加可能的PLA功能的数量，从而为PLA提供改进的功能密度。 控制电路基本上由两级AND-OR电路组成，与PLA的AND和OR阵列技术完全兼容。 为了最佳利用“无关位置”和“飞机”，每个功能输入可以切换到解放军的任意功能。 通过在OR阵列中提供一个附加控制线，整个OR阵列的控制逻辑减少到只有两个与门。

公开(公告)号：US4380811A

公开(公告)日：1983-04-19

申请号：US254027

申请日：1981-04-14

申请人： Volkmar Gotze ,  Dieter Schutt

发明人： Volkmar Gotze ,  Dieter Schutt

IPC分类号： G06F7/00 ,  G01R31/3185 ,  G06F11/20 ,  H03K19/177 ,  G01R31/28 ,  G11C29/00

CPC分类号： H03K19/17712 ,  G01R31/318516 ,  H03K19/17764

摘要： An apparatus and a method to automatically locate defects and to automatically insert and personalize dummy lines in a PLA having latches controlling the cross points of the AND and OR array. Upon occurrence of an error in the PLA, a check signal is generated which interrupts normal operation of the PLA and which initiates a test procedure. The cross point latches are automatically loaded with test patterns and the output of the PLA is analyzed to locate the defective part, for example, a damaged cross point transistor, short circuited or open line. The dummy lines are repersonalized automatically to replace lines which are defective themselves or which are connected to defective crosspoints.

摘要翻译： 自动定位缺陷的装置和方法，并自动插入和个性化在具有控制AND和OR阵列的交叉点的锁存器的PLA中的虚拟线。 在PLA中发生错误时，产生一个中断PLA的正常操作并启动测试程序的检查信号。 交叉点锁存器自动加载测试图案，并分析PLA的输出以定位故障部分，例如损坏的交叉晶体管，短路或开路线。 虚拟线路将自动进行个性化，以替换自身有缺陷或连接到有缺陷的交叉点的线路。

公开(公告)号：US5941966A

公开(公告)日：1999-08-24

申请号：US842468

申请日：1997-05-05

申请人： Volkmar Gotze ,  Martin Neumann

发明人： Volkmar Gotze ,  Martin Neumann

IPC分类号： G06F13/38 ,  G06F9/00

CPC分类号： G06F13/387

摘要： The invention relates to a device and a process for the control of a data transmission channel or data bus, in particular a data bus on which the data is transmitted in a bit serial fashion according to a prescribed transmission protocol or bus protocol. The multitude of data buses which currently exist or will be developed in the future have their own proprietary data bus protocols and this means that for almost every data bus a special control device is required. The invention just described permits a multitude of data buses to be controlled by using a hierarchical processor architecture with at least two processor levels, which are respectively optimized for specific control tasks. The invention can be used for the control of a multitude of data buses, on which data is transmitted according to different transmission protocols. The invention is particularly suitable for the control of a multitude of field data buses or field buses for general applications, and in particular for the control of field buses in motor vehicles, such as ABUS, CAN bus, SAE bus J1850 or VAN bus.

摘要翻译： 本发明涉及一种用于控制数据传输信道或数据总线，特别是其上根据规定的传输协议或总线协议以比特串行方式发送数据的数据总线的装置和方法。 目前存在或将来将要开发的大量数据总线具有自己的专有数据总线协议，这意味着对于几乎每个数据总线，都需要一个特殊的控制设备。 刚刚描述的本发明允许通过使用具有至少两个处理器级别的分级处理器架构来控制多个数据总线，其分别针对特定控制任务优化。 本发明可用于控制多个数据总线，根据不同的传输协议传输数据。 本发明特别适用于多种现场数据总线或现场总线的控制，用于一般应用，特别是用于控制诸如ABUS，CAN总线，SAE总线J1850或VAN总线的机动车辆中的现场总线。

公开(公告)号：US06466216B1

公开(公告)日：2002-10-15

申请号：US08737300

申请日：1996-10-11

申请人： Volkmar Gotze ,  Martin Neumann

发明人： Volkmar Gotze ,  Martin Neumann

IPC分类号： G06F1500

CPC分类号： G09G5/001 ,  G06F3/14 ,  G09G2360/126

摘要： A computer system having an optimized display controller is disclosed. The computer system has a central processing unit connected to a system bus. Within the computer system, both a system memory and a video memory are connected in parallel to the system bus. In addition, the computer system also includes a display controller that is connected only between the system bus and a video display.

摘要翻译： 公开了一种具有优化的显示控制器的计算机系统。 计算机系统具有连接到系统总线的中央处理单元。 在计算机系统内，系统存储器和视频存储器与系统总线并联连接。 此外，计算机系统还包括仅在系统总线和视频显示器之间连接的显示控制器。

公开(公告)号：US4450561A

公开(公告)日：1984-05-22

申请号：US358737

申请日：1982-03-16

申请人： Volkmar Gotze ,  Gunther Potz

发明人： Volkmar Gotze ,  Gunther Potz

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/19

CPC分类号： H03M13/19 ,  G06F11/10

摘要： Each of the check bits of an ECC codeword is generated in parallel in a byte serial sequence to permit structuring of the ECC device so that it has general application. For this purpose a byte wide check bit generator is provided for each of the check bits. These check bit generators contain generalized gating logic controlled by stored data that is capable of passing any combination of the bits making up the byte. As each byte enters such a check bit generator, the data controlling the gating logic is changed to generate a partial sum of the check bit using only those data bits from that data byte designated by the H matrix on the ECC. The partial check bits are then accumulated modulo 2 to generate the check bit to be stored with the data bits.

摘要翻译： ECC码字的每个校验位以字节串行序列并行生成，以允许构造ECC设备，使其具有一般应用。 为此，为每个校验位提供字节宽检查位发生器。 这些检查位发生器包含通过存储数据控制的通用门控逻辑，该数据能够通过构成字节的位的任何组合。 当每个字节进入这样的校验位发生器时，控制门控逻辑的数据被改变，以便仅使用由ECC上的H矩阵指定的数据字节的那些数据位产生校验位的部分和。 然后，部分校验位以模2积累，以产生要与数据位一起存储的校验位。