公开(公告)号：US5995425A

公开(公告)日：1999-11-30

申请号：US898826

申请日：1997-07-23

申请人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi ,  Albert Thomas Williams

发明人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi ,  Albert Thomas Williams

IPC分类号： G01R31/3185 ,  G11C7/00

CPC分类号： G01R31/318536 ,  Y10S257/903

摘要： A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.

摘要翻译： 硬件设计技术允许检查具有嵌入式阵列和寄存器的大型宏的元素和原理图的设计系统语言（DSL）规范。 硬件组织将逻辑验证的CPU时间缩小到指数级数量级，而不会引发验证过程或逻辑仿真。 硬件组织由水平字层而不是位级组成。 使用布尔形式难以提取的元素的消除过程可以验证存储器结构周围和内部的逻辑。 结果寄存器阵列硬件组织可以验证所有引脚和网络直到存储元件。

公开(公告)号：US5973529A

公开(公告)日：1999-10-26

申请号：US778854

申请日：1997-01-06

申请人： Terry Ivan Chappell ,  Walter Harvey Henkels ,  Wei Hwang ,  Rajiv Vasant Joshi

发明人： Terry Ivan Chappell ,  Walter Harvey Henkels ,  Wei Hwang ,  Rajiv Vasant Joshi

IPC分类号： H03K3/037 ,  H03K3/289

CPC分类号： H03K3/0375

摘要： A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

摘要翻译： 公开了一种低功率脉冲到静态转换锁存电路。 该电路包括自定时控制和使用自复位CMOS电路技术设计的n位锁存阵列。 控制器的自定时功能只需要一个系统时钟输入。 评估，复位和写使能控制都在控制宏中生成。 锁存器是电平敏感扫描设计（LSSD）兼容的，并符合自复位CMOS（SCRMOS）测试模式。 这些锁存器的使用有助于采用静态和动态电路的混合来实现高性能的高级数字系统的同步，流水线操作，电源管理和测试。

公开(公告)号：US06279144B1

公开(公告)日：2001-08-21

申请号：US09377389

申请日：1999-08-19

申请人： Walter Harvey Henkels ,  Wei Hwang ,  Rajiv Vasant Joshi ,  Albert Thomas Williams

发明人： Walter Harvey Henkels ,  Wei Hwang ,  Rajiv Vasant Joshi ,  Albert Thomas Williams

IPC分类号： G06F1750

CPC分类号： G01R31/318536 ,  Y10S257/903

摘要： A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. A memory array cell comprises a pair of cross-coupled inverters forming a first latch for storing data. The first latch has an output connected to a read bit line. True and complement write word and bit line input to the first latch. A first set of pass gates connects between the true and complement write word and bit line inputs via gates and the input of said first latch. The first set of pass gates is responsive to a first clock via a second pass gate. A pair of cross-coupled inverters forms a second latch of a Level Sensitive Scan Design (LSSD). The second latch has output connected to an LSSD output for design verification. A second pass gate connects between the output of the first set of pass gates and the input of said first latch. The second pass gate is responsive to said first clock. A third pass gate connects between the output of said first latch and the input of said second latch. The third pass gate is responsive to a second clock. The first and second clocks are responsive to a black boxing process for incremental verification.

摘要翻译： 硬件设计技术允许检查具有嵌入式阵列和寄存器的大型宏的元素和原理图的设计系统语言（DSL）规范。 硬件组织将逻辑验证的CPU时间缩小到指数级数量级，而不会引发验证过程或逻辑仿真。 硬件组织由水平字层而不是位级组成。 存储器阵列单元包括一对交叉耦合的反相器，形成用于存储数据的第一锁存器。 第一个锁存器具有连接到读取位线的输出。 将第一个锁存器的写入字和位线输入为真和补码。 第一组通过门通过门和所述第一锁存器的输入连接在真和补写写字和位线输入之间。 第一组传递门通过第二传递门响应于第一时钟。 一对交叉耦合的反相器形成了级别敏感扫描设计（LSSD）的第二个锁存器。 第二个锁存器具有输出连接到LSSD输出，用于设计验证。 第二传递门连接在第一组通过门的输出和所述第一锁存器的输入之间。 第二传递门响应于所述第一时钟。 第三传输门连接在所述第一锁存器的输出端和所述第二锁存器的输入端之间。 第三传递门响应第二个时钟。 第一和第二时钟响应于黑色加密处理以进行增量验证。

公开(公告)号：US5939898A

公开(公告)日：1999-08-17

申请号：US881265

申请日：1997-06-24

申请人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi

发明人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi

IPC分类号： H03K19/096 ,  H03K19/00

CPC分类号： H03K19/096 ,  H03K19/0966

摘要： Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level. The interfaces of all self-resetting macros in accordance with the teachings of the invention have no need for a handshake circuit or interlock circuits.

摘要翻译： 非常快速的非常大规模的集成（VLSI）芯片可以由“自复位”或“自定时”宏构建。 输入隔离器电路提供有效的输入隔离/去耦，其允许输入脉冲宽度在宽范围内变化。 这避免了对于具有许多宏的大芯片，确保一个宏的输出符合接收宏的输入要求的重大问题。 使用混合静态和动态电路。 该电路包括三个阶段。 输入第一级是提供脉冲切断功能的静态NOR电路。 该第一阶段将任何太宽的输入脉冲切除到期望的脉冲宽度。 中间阶段是一种自复位互补金属氧化物半导体（SRCMOS）动态NOR电路，用于捕获复位过快的输入。 最后一个阶段是将动态节点保持在恒定输出电压电平的半锁存电路。 根据本发明的教导，所有自复位宏的接口不需要握手电路或互锁电路。

公开(公告)号：US6151266A

公开(公告)日：2000-11-21

申请号：US943738

申请日：1997-10-03

申请人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi

发明人： Walter Harvey Henkels, deceased ,  Wei Hwang ,  Rajiv Vasant Joshi

IPC分类号： G06F9/30 ,  G06F9/38 ,  G11C8/16 ,  G11C8/00

CPC分类号： G06F9/30141 ,  G06F9/3869 ,  G11C8/16

摘要： Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in effective input isolation scheme.

摘要翻译： 公开了用于高性能异步多端口寄存器文件的自复位和写控制电路。 高速写入操作通过静态数据输入和动态数据控制电路的组合来实现。 写时序信号产生，真实和补码地址缓冲器，解码器和字线驱动器以及写使能电路采用具有自复位互补金属氧化物半导体（SRCMOS）电路技术的完全定制设计的方法的优点。 施加到多端口寄存器单元的相应输入端口的单独写使能脉冲对于在这些输入端口之间建立优先级是有效的。 在这种设计中，当写入端口寻址同一个寄存器时，建立B写入端口对A写入端口的优先级。 本发明提供一种有效的输入隔离/去耦电路技术，其允许输入脉冲宽度在宽范围内变化。 这允许写入操作对控制脉冲宽度不敏感，从而产生有效的输入隔离方案。

公开(公告)号：US5780335A

公开(公告)日：1998-07-14

申请号：US638531

申请日：1996-04-26

申请人： Walter Harvey Henkels ,  Wei Hwang

发明人： Walter Harvey Henkels ,  Wei Hwang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/108

摘要： A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

摘要翻译： 相对于位线对和单个字线配置的两晶体管一电容器DRAM单元，其中两个晶体管的栅极连接到单个字线，并且每个晶体管的源极/漏极之一连接到相应的 电容器的电极和晶体管的源极/漏极中的另一个连接到互补位线对的相应位线。 存储电容器是三维结构，其中两个电极与所有其它电池存储电容器的电极电绝缘。 公开了一种堆叠的沟槽电池制造设计，其具有用于将外部电极连接到一个晶体管的扩散区域的掩埋带和用于将内部电极连接到第二存取晶体管的扩散区域的表面带。