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    LLR COMPUTATION DEVICE AND ERROR CORRECTION DECODING DEVICE
    1.
    发明申请
    LLR COMPUTATION DEVICE AND ERROR CORRECTION DECODING DEVICE 有权
    LLR计算设备和错误校正解码设备

    公开(公告)号：US20140229805A1

    公开(公告)日：2014-08-14

    申请号：US14343305

    申请日：2012-10-05

    申请人： Kenya Sugihara ,  Wataru Matsumoto

    发明人： Kenya Sugihara ,  Wataru Matsumoto

    IPC分类号： H04L1/00

    CPC分类号： H04L1/0045 ,  H03M13/1102 ,  H03M13/612 ,  H03M13/6337 ,  H04L1/005 ,  H04L1/0057 ,  H04L25/067 ,  H04L27/38 ,  H04L2025/0342

    摘要： A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.

    摘要翻译： 双参考点对确定单元101通过选择两个传输符号点来确定两个参考点对，其LLR计算目标位为0，两个传输符号点的LLR计算目标位为1.LLR计算单元113分配 分别为两个参考点对计算的两个LLR的权重，然后将它们相加，并且进一步向加法结果添加可能为零的校正项，从而计算两个参考点对的LLR。

    Decoding apparatus and communications apparatus
    2.
    发明授权
    Decoding apparatus and communications apparatus 有权
    解码装置和通信装置

    公开(公告)号：US08201047B2

    公开(公告)日：2012-06-12

    申请号：US11791996

    申请日：2005-12-01

    申请人： Rui Sakai ,  Wataru Matsumoto ,  Yoshikuni Miyata ,  Hideo Yoshida ,  Takahiko Nakamura

    发明人： Rui Sakai ,  Wataru Matsumoto ,  Yoshikuni Miyata ,  Hideo Yoshida ,  Takahiko Nakamura

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1188 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/3911 ,  H03M13/6583 ,  H04L1/005 ,  H04L1/0057

    摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

    摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。

    Check matrix generating device, check matrix generating method, encoder, transmitter, decoder, and receiver
    3.
    发明授权
    Check matrix generating device, check matrix generating method, encoder, transmitter, decoder, and receiver 有权
    检查矩阵生成装置，校验矩阵生成方法，编码器，发送器，解码器和接收器

    公开(公告)号：US08196014B2

    公开(公告)日：2012-06-05

    申请号：US12667002

    申请日：2008-06-26

    申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

    发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

    IPC分类号： H03M13/00

    CPC分类号： H03M13/116 ,  H03M13/118

    摘要： When arranging J cyclic permutation matrices I(pj,l) with p rows and q columns (0≦j≦J−1, 0≦l≦L−1) in a row direction and also arranging L cyclic permutation matrices I(pj,l) in a column direction so as to generate a regular quasi-cyclic matrix having uniform row and column weights, a quasi-cyclic matrix generating unit 31 configures the regular quasi-cyclic matrix by combining cyclic permutation matrices I(pj,l) in each of which matrix elements whose row number is r (0≦r≦p−1) and whose column number is (r+pj,l) mod p are “1”s, and other matrix elements are “0”s in such a way that a plurality of cyclic permutation matrices I(pj,l) arranged at, e.g., the 1st row differ from one another.

    摘要翻译： 当在行方向上布置具有p行和q列（0＆nlE; j＆nlE; J-1,0＆nlE; l＆nlE; L-1）的J个循环置换矩阵I（pj，l）时，并且还排列L个循环置换矩阵I（pj， 1）在列方向上，以便产生具有均匀行和列权重的规则准循环矩阵，准循环矩阵生成单元31通过将循环置换矩阵I（pj，l）组合在一起，构成规则准循环矩阵 其行号为r（0＆nlE; r＆nlE; p-1）并且列数为（r + pj，l）mod p的矩阵元素中的每一个为“1”，其他矩阵元素为“0” 布置在例如第一行的多个循环置换矩阵I（pj，l）彼此不同的方式。

    Communication apparatus and decoding method
    4.
    发明授权
    Communication apparatus and decoding method 有权
    通信设备和解码方法

    公开(公告)号：US08132080B2

    公开(公告)日：2012-03-06

    申请号：US11988565

    申请日：2006-07-12

    申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida ,  Yoshikuni Miyata

    发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida ,  Yoshikuni Miyata

    IPC分类号： H03M13/45

    CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6561 ,  H03M13/658 ,  H03M13/6583

    摘要： A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

    摘要翻译： 通信装置包括存储单元，行处理单元和列处理单元。 行处理单元重复执行行处理，以计算校验矩阵中的每列和每行的列处理LLR。 列处理单元针对每个列和校验矩阵的每一行计算行处理LLR，并且重复执行列处理，以在存储单元中存储行处理LLR的绝对值的最小值k。 行处理单元和列处理单元交替执行其处理。 行处理单元使用近似最小值执行计算，而列处理单元循环地更新每行的最小k值。

    CODING APPARATUS, CODING METHOD, CODING AND DECODING APPARATUS, AND COMMUNICATION APPARATUS
    6.
    发明申请
    CODING APPARATUS, CODING METHOD, CODING AND DECODING APPARATUS, AND COMMUNICATION APPARATUS 审中-公开
    编码装置，编码方法，编码和解码装置以及通信装置

    公开(公告)号：US20100070820A1

    公开(公告)日：2010-03-18

    申请号：US12516810

    申请日：2007-12-14

    申请人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

    发明人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

    IPC分类号： H03M13/05

    CPC分类号： H03M13/116 ,  H03M13/6362

    摘要： When carrying out puncturing of some redundant bits in an LDPC code having a check matrix of QC structure and LDGM structure, a puncture rule for preventing redundant bits which are chained to one another from being punctured is set up, and some redundant bits out of an LDPC-coded signal are punctured out of the LDPC-coded signal according to the puncture rule. As a result, redundant bits which are chained to one another can be left.

    摘要翻译： 当在具有QC结构和LDGM结构的校验矩阵的LDPC码中执行一些冗余位的删截时，建立用于防止相互链接的冗余位被打孔的穿孔规则，并且从 根据穿孔规则，从LDPC编码信号中删除LDPC编码信号。 结果，可以留下彼此链接的冗余位。

    RETRANSMISSION CONTROL METHOD AND COMMUNICATIONS DEVICE
    7.
    发明申请
    RETRANSMISSION CONTROL METHOD AND COMMUNICATIONS DEVICE 审中-公开
    重新设计控制方法和通信设备

    公开(公告)号：US20100005361A1

    公开(公告)日：2010-01-07

    申请号：US12559169

    申请日：2009-09-14

    申请人： Wataru Matsumoto

    发明人： Wataru Matsumoto

    IPC分类号： H04L1/08 ,  H03M13/05 ,  G06F11/10 ,  G06F11/14

    CPC分类号： H03M13/1148 ,  H03M13/1151 ,  H03M13/6306 ,  H03M13/6393 ,  H04L1/0057 ,  H04L1/08 ,  H04L1/1607 ,  H04L1/1819

    摘要： A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix; transmitting the codeword generated by using the generator matrix to another communications device; generating, when the communications device receives a NAK in response to the codeword, a first additional parity by using the second parity check matrix; and retransmitting the first additional parity to the another communications device.

    摘要翻译： 一种重传控制方法，包括：产生N个奇偶校验矩阵; 生成包含第一奇偶校验矩阵中包含的校验符号生成矩阵的生成矩阵; 将通过使用所述生成矩阵生成的码字发送到另一通信设备; 当所述通信设备响应于所述码字接收到NAK时，产生通过使用所述第二奇偶校验矩阵的第一附加奇偶校验; 并向另一个通信设备重发第一附加奇偶校验。

    CHECK MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION DEVICE, ENCODER, AND DECODER
    10.
    发明申请
    CHECK MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION DEVICE, ENCODER, AND DECODER 审中-公开
    检查矩阵生成方法，编码方法，解码方法，通信设备，编码器和解码器

    公开(公告)号：US20090063930A1

    公开(公告)日：2009-03-05

    申请号：US12278185

    申请日：2007-01-31

    申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

    发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

    IPC分类号： H03M13/03 ,  G06F11/10

    CPC分类号： H03M13/116 ,  H03M13/1102 ,  H03M13/118

    摘要： A regular quasi-cyclic matrix is generated with cyclic permutation matrices and specific regularity given to the cyclic permutation matrices. A mask matrix for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. An irregular masked quasi-cyclic matrix is generated by converting a specific cyclic permutation matrix in the regular quasi-cyclic matrix into a zero-matrix using a mask matrix supporting a specific encoding rate. An irregular parity check matrix with an LDGM structure is generated with a masked quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner.

    摘要翻译： 生成具有循环置换矩阵和赋予循环置换矩阵的特定规则性的规则准循环矩阵。 产生用于使正规准循环矩阵成为不规则准循环矩阵的掩模矩阵。 通过使用支持特定编码速率的掩码矩阵将常规准循环矩阵中的特定循环置换矩阵转换为零矩阵来生成不规则掩蔽准循环矩阵。 生成具有LDGM结构的不规则奇偶校验矩阵，其具有掩蔽的准循环矩阵和其中循环置换矩阵以阶梯状排列的矩阵。