-
公开(公告)号：US08201047B2
公开(公告)日：2012-06-12
申请号：US11791996
申请日：2005-12-01
IPC分类号： H03M13/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。
-
2.发明授权Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder 有权测试矩阵生成方法，编码方法，解码方法，通信装置，通信系统，编码器和解码器公开(公告)号：US08103935B2
公开(公告)日：2012-01-24
申请号：US12063507
申请日：2006-07-31
IPC分类号： G06F11/00
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译： 准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵， 产生重量分布。 特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。 其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。
-
3.发明申请TEST MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ENCODER AND DECODER 有权测试矩阵生成方法，编码方法，解码方法，通信设备，通信系统，编码器和解码器公开(公告)号：US20090265600A1
公开(公告)日：2009-10-22
申请号：US12063507
申请日：2006-07-31
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译： 准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵， 产生重量分布。 特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。 其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。
-
公开(公告)号：US20080246639A1
公开(公告)日：2008-10-09
申请号：US11791996
申请日：2005-12-01
IPC分类号： H03M7/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。
-
5.发明授权Error correction encoding method and apparatus, and error correction decoding method and apparatus 失效纠错编码方法和装置，以及纠错解码方法和装置公开(公告)号：US06912684B2
公开(公告)日：2005-06-28
申请号：US10097347
申请日：2002-03-15
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.
摘要翻译： 提供纠错编码方法和装置以及纠错解码方法和装置，而不需要传输尾比特。 包括turbo编码步骤（ST 41 -ST 45）和发送终止处理步骤（ST 46-> ST 44 -ST 47）。 在turbo编码步骤中，发送信息比特序列被分成多个帧。 每个递归系统卷积编码器中的寄存器在第一帧的turbo编码之前被初始化。 在执行第一帧的turbo编码之后，在第二帧和后续帧的turbo编码之前，第二帧和后续帧被连续地进行turbo编码，而不在每个递归系统卷积编码器中初始化寄存器。 在传输终止处理步骤中，仅在最后一帧已进行turbo编码之后才计算用于初始化每个递归系统卷积编码器中的寄存器的尾比特。
-
6.发明授权Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权多重编码方法和装置，多重解码方法和装置以及信息传输系统公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译： 多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。 交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。 交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。 然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。
-
公开(公告)号：US07069496B2
公开(公告)日：2006-06-27
申请号：US10284391
申请日：2002-10-31
IPC分类号： H03M13/00
CPC分类号： H04L1/0066 , H03M13/136 , H03M13/151 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/3738 , H03M13/45 , H03M13/451 , H03M13/6306 , H03M13/6561 , H04L1/005 , H04L1/1835 , H04L1/1874
摘要： A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.
-
公开(公告)号：US20140136931A1
公开(公告)日：2014-05-15
申请号：US14129220
申请日：2012-06-26
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , H03M13/159
摘要： Provided is an error-correcting decoder including: a syndrome generation unit for calculating, as a syndrome, coefficients of a residual polynomial that are obtained by dividing received data by a generator polynomial; information bit error pattern generation unit for generating all error patterns of information bits; a check bit error pattern generation unit for calculating, for each of the error patterns of the information bits, an error pattern of check bits based on the syndrome value; and an error correction unit for correcting the error pattern generated for a combination of codes having a weight of the error patterns of the information bits and the check bits smaller than a threshold value.
摘要翻译： 提供了一种纠错解码器，包括：校正子生成单元，用于计算通过将接收数据除以生成多项式而获得的残差多项式的系数作为校正子; 信息比特错误模式生成单元，用于生成信息比特的所有错误模式; 检查比特错误模式生成单元，用于针对所述信息比特的每个错误模式，基于所述校正子值计算校验比特的错误模式; 以及纠错单元，用于校正对具有信息比特的误差模式的权重和小于阈值的校验比特的代码的组合生成的错误模式。
-
9.发明授权Error-correcting decoder continuously adding flag signals to locations preceding a first location at which a difference between path metrics is lower than the threshold 失效误差校正解码器连续地将标志信号添加到路径度量之间的差异低于阈值的第一位置之前的位置
公开(公告)号：US6108811A
公开(公告)日：2000-08-22
申请号：US944292
申请日：1997-10-06
申请人： Takahiko Nakamura , Hideo Yoshida , Hachiro Fujita
发明人： Takahiko Nakamura , Hideo Yoshida , Hachiro Fujita
CPC分类号： H04L1/0066 , H03M13/00 , H03M13/4161 , H04L1/0054 , H04L1/0065
摘要： In an error-correcting decoder, in which an input digital signal including reliability information is decoded by using a Viterbi algorithm as a first decoding process and a final decoded result is obtained by block-code decoding as a second decoding process, a flag signal is added to a location where a value of reliability of path metric determined by the Viterbi algorithm is lower than a threshold, as an original flagged location. A flag signal adding unit continuously adds flag signals to locations, from the original flagged location to locations preceding the originally flagged location, after back tracing. The flagged locations are then regarded as erasure locations in the block-code decoding process.
摘要翻译： 在通过使用维特比算法作为第一解码处理对包含可靠性信息的输入数字信号进行解码的纠错解码器中，通过作为第二解码处理的块码解码得到最终的解码结果，标志信号为 添加到由维特比算法确定的路径度量的可靠性值低于阈值的位置，作为原始标记位置。 标记信号添加单元连续地将标记信号从原始标记位置添加到在原始标记位置之前的位置之后的后跟踪。 标记位置在块码解码处理中被视为擦除位置。
-
10.发明授权Turbo-code error correcting decoder, turbo-code error correction decoding method, turbo-code decoding apparatus, and turbo-code decoding system 失效Turbo码纠错解码器，Turbo码纠错解码方法，Turbo码解码装置和Turbo码解码系统公开(公告)号：US06757865B1
公开(公告)日：2004-06-29
申请号：US09568163
申请日：2000-05-10
申请人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
发明人： Takahiko Nakamura , Hachiro Fujita , Hideo Yoshida
IPC分类号： H03M1303
CPC分类号： H03M13/4146 , H03M13/2957 , H03M13/3905 , H03M13/3972
摘要： In a conventional turbo-code decoding apparatus, there is a need for calculating a state transition probability for MAP decoding of convolutional codes composing turbo codes in an error correcting decoder and a channel state needs to be measured based on soft decision information to calculate the probability, by which an arithmetic operation amount is enormously increased. Turbo-code error correction decoding is performed by executing operations in a branch metric based forward path metric calculation step of calculating a forward path metric based on a branch metric with calculating the branch metric for a transition to an adjacent time point and a soft decision information calculation step of calculating N bits of soft decision information based on the branch metric, the forward path metric, and a backward path metric with calculating the backward path metric based on the branch metric.
摘要翻译： 在常规turbo码解码装置中，需要计算在纠错解码器中构成turbo码的卷积码的MAP解码的状态转移概率，而需要根据软决策信息来测量信道状态，以计算概率 通过在基于分支度量的前向路径度量计算步骤中执行基于分支度量计算前向路径量度的操作来执行Turbo码纠错解码，计算分支度量用于 过渡到相邻时间点，以及软判决信息计算步骤，基于分支度量，前向路径度量和反向路径度量，基于分支度量计算反向路径度量来计算软判决信息的N位。
-
-
-
-
-
-
-
-
-
搜索结果
67 条记录 (耗时 0.037 秒)
