公开(公告)号：US20100070820A1

公开(公告)日：2010-03-18

申请号：US12516810

申请日：2007-12-14

申请人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

发明人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

IPC分类号： H03M13/05

CPC分类号： H03M13/116 ,  H03M13/6362

摘要： When carrying out puncturing of some redundant bits in an LDPC code having a check matrix of QC structure and LDGM structure, a puncture rule for preventing redundant bits which are chained to one another from being punctured is set up, and some redundant bits out of an LDPC-coded signal are punctured out of the LDPC-coded signal according to the puncture rule. As a result, redundant bits which are chained to one another can be left.

摘要翻译： 当在具有QC结构和LDGM结构的校验矩阵的LDPC码中执行一些冗余位的删截时，建立用于防止相互链接的冗余位被打孔的穿孔规则，并且从 根据穿孔规则，从LDPC编码信号中删除LDPC编码信号。 结果，可以留下彼此链接的冗余位。

公开(公告)号：US20090138785A1

公开(公告)日：2009-05-28

申请号：US12293355

申请日：2007-03-15

申请人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

发明人： Lui Sakai ,  Wataru Matsumoto ,  Hideo Yoshida

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/1185 ,  H03M13/1102 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/353 ,  H03M13/356 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6393 ,  H03M13/6527 ,  H03M13/6544 ,  H04L1/0057 ,  H04L1/0068 ,  H04L1/0083 ,  H04L1/1819

摘要： A communication device that transmits and receives LDPC-encoded information by using MIMO technology. The communication device includes a transmission sorting unit that sorts LDPC-encoded bits constituting the LDPC-encoded information in a descending order of column degree of a check matrix used for generating the LDPC-encoded bits; and a signal transmitting unit that transmits the LDPC-encoded bits sorted by the transmission sorting unit by allocating the LDPC-encoded bits from a transmission line having a lower noise level in sorted order.

摘要翻译： 一种使用MIMO技术发送和接收LDPC编码信息的通信装置。 通信装置包括发送分类单元，按照用于生成LDPC编码比特的校验矩阵的列顺序对构成LDPC编码信息的LDPC编码比特进行排序; 以及信号发送单元，其通过按照排序顺序从具有较低噪声电平的传输线分配LDPC编码比特来发送由发送分类单元排序的LDPC编码比特。

公开(公告)号：US20100272202A1

公开(公告)日：2010-10-28

申请号：US12810638

申请日：2008-12-25

申请人： Wataru Matsumoto ,  Shigeru Uchida ,  Toshiyuki Kuze ,  Hideo Yoshida

发明人： Wataru Matsumoto ,  Shigeru Uchida ,  Toshiyuki Kuze ,  Hideo Yoshida

IPC分类号： H04L27/28

CPC分类号： H04L1/1812 ,  H04B7/0413 ,  H04L1/0656 ,  H04L1/1816

摘要： When an error correction decoding unit 26 of a data reception device 2 fails in error correction decoding of a codeword, an MIMO processing unit 15 of a data transmission device 1 deforms transmitted codewords according to a predetermined rule, and transmits the codewords, and the error correction decoding unit 26 of the data reception device 2 reproduces data by using the deformed codewords. As a result, not only the noise but the interference wave components can be reduced, and the success rates of the demodulation and error correction decoding can be improved greatly.

摘要翻译： 当数据接收装置2的纠错解码单元26对码字的纠错解码失败时，数据传输装置1的MIMO处理单元15根据预定规则使发送的码字变形，并发送码字，并且发送错误 数据接收装置2的校正解码单元26通过使用变形的码字再现数据。 结果，不仅可以降低噪声而且可以降低干扰波分量，而且可以大大提高解调和纠错解码的成功率。

公开(公告)号：US20100058140A1

公开(公告)日：2010-03-04

申请号：US12376344

申请日：2007-08-02

申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1177 ,  H03M13/6508

摘要： A regular quasi-cyclic matrix is generated in which specific regularity is given to cyclic permutation matrices. A mask matrix capable of supporting a plurality of encoding rates is generated. A specific cyclic permutation matrix in the regular quasi-cyclic matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix with an LDGM structure is generated in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

摘要翻译： 生成规则准循环矩阵，其中给定循环置换矩阵的特定规则性。 产生能够支持多种编码速率的掩模矩阵。 使用与特定编码速率相对应的掩模矩阵将常规准循环矩阵中的特定循环置换矩阵转换为零矩阵，以生成不规则掩蔽准循环矩阵。 生成具有LDGM结构的不规则奇偶校验矩阵，其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置。

公开(公告)号：US20130311847A1

公开(公告)日：2013-11-21

申请号：US13982919

申请日：2012-05-30

申请人： Yoshikuni Miyata ,  Wataru Matsumoto ,  Hideo Yoshida ,  Kazuo Kubo

发明人： Yoshikuni Miyata ,  Wataru Matsumoto ,  Hideo Yoshida ,  Kazuo Kubo

IPC分类号： H03M13/29

CPC分类号： H03M13/29 ,  H03M13/1102 ,  H03M13/1145 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/356

摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

摘要翻译： 提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时 通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中， 根据发生的过量或不足，进行非均匀分配。

公开(公告)号：US20100211846A1

公开(公告)日：2010-08-19

申请号：US12667002

申请日：2008-06-26

申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/118

摘要： When arranging J cyclic permutation matrices I(pj,l) with p rows and q columns (0≦j≦J−1, 0≦l≦L−1) in a row direction and also arranging L cyclic permutation matrices I(pj,l) in a column direction so as to generate a regular quasi-cyclic matrix having uniform row and column weights, a quasi-cyclic matrix generating unit 31 configures the regular quasi-cyclic matrix by combining cyclic permutation matrices I(pj,l) in each of which matrix elements whose row number is r (0≦r≦p−1) and whose column number is (r+pj,l) mod p are “1”s, and other matrix elements are “0”s in such a way that a plurality of cyclic permutation matrices I(pj,l) arranged at, e.g., the 1st row differ from one another.

摘要翻译： 当在行方向上布置具有p行和q列（0＆nlE; j＆nlE; J-1,0＆nlE; l＆nlE; L-1）的J个循环置换矩阵I（pj，l）时，并且还排列L个循环置换矩阵I（pj， 1）在列方向上，以便产生具有均匀行和列权重的规则准循环矩阵，准循环矩阵生成单元31通过将循环置换矩阵I（pj，l）组合在一起，构成规则准循环矩阵 其行号为r（0＆nlE; r＆nlE; p-1）并且列数为（r + pj，l）mod p的矩阵元素中的每一个为“1”，其他矩阵元素为“0” 布置在例如第一行的多个循环置换矩阵I（pj，l）彼此不同的方式。

公开(公告)号：US20090164864A1

公开(公告)日：2009-06-25

申请号：US12097390

申请日：2006-12-13

申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/118 ,  H03M13/1185

摘要： A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking qc matrix. An irregular parity check matrix with a LDGM structure is generated, in which the masking qc matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.

摘要翻译： 生成常规的qc矩阵，其中具有特定规则性的循环置换矩阵被排列在行和列方向上。 生成支持多个编码率的掩码矩阵，使常规的qc矩阵变为不规则的。 使用对应于特定编码率的掩码矩阵将常规qc矩阵中的特定循环置换矩阵转换为零矩阵以生成不规则掩蔽qc矩阵。 生成具有LDGM结构的不规则奇偶校验矩阵，其中掩蔽qc矩阵和其中循环置换矩阵以阶梯排列的矩阵排列在预定位置。

公开(公告)号：US08201047B2

公开(公告)日：2012-06-12

申请号：US11791996

申请日：2005-12-01

申请人： Rui Sakai ,  Wataru Matsumoto ,  Yoshikuni Miyata ,  Hideo Yoshida ,  Takahiko Nakamura

发明人： Rui Sakai ,  Wataru Matsumoto ,  Yoshikuni Miyata ,  Hideo Yoshida ,  Takahiko Nakamura

IPC分类号： H03M13/00

CPC分类号： H03M13/1188 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/3911 ,  H03M13/6583 ,  H04L1/005 ,  H04L1/0057

摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。

公开(公告)号：US08196014B2

公开(公告)日：2012-06-05

申请号：US12667002

申请日：2008-06-26

申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida

IPC分类号： H03M13/00

CPC分类号： H03M13/116 ,  H03M13/118

摘要： When arranging J cyclic permutation matrices I(pj,l) with p rows and q columns (0≦j≦J−1, 0≦l≦L−1) in a row direction and also arranging L cyclic permutation matrices I(pj,l) in a column direction so as to generate a regular quasi-cyclic matrix having uniform row and column weights, a quasi-cyclic matrix generating unit 31 configures the regular quasi-cyclic matrix by combining cyclic permutation matrices I(pj,l) in each of which matrix elements whose row number is r (0≦r≦p−1) and whose column number is (r+pj,l) mod p are “1”s, and other matrix elements are “0”s in such a way that a plurality of cyclic permutation matrices I(pj,l) arranged at, e.g., the 1st row differ from one another.

摘要翻译： 当在行方向上布置具有p行和q列（0＆nlE; j＆nlE; J-1,0＆nlE; l＆nlE; L-1）的J个循环置换矩阵I（pj，l）时，并且还排列L个循环置换矩阵I（pj， 1）在列方向上，以便产生具有均匀行和列权重的规则准循环矩阵，准循环矩阵生成单元31通过将循环置换矩阵I（pj，l）组合在一起，构成规则准循环矩阵 其行号为r（0＆nlE; r＆nlE; p-1）并且列数为（r + pj，l）mod p的矩阵元素中的每一个为“1”，其他矩阵元素为“0” 布置在例如第一行的多个循环置换矩阵I（pj，l）彼此不同的方式。

公开(公告)号：US08132080B2

公开(公告)日：2012-03-06

申请号：US11988565

申请日：2006-07-12

申请人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida ,  Yoshikuni Miyata

发明人： Wataru Matsumoto ,  Rui Sakai ,  Hideo Yoshida ,  Yoshikuni Miyata

IPC分类号： H03M13/45

CPC分类号： H03M13/1122 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/6561 ,  H03M13/658 ,  H03M13/6583

摘要： A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.

摘要翻译： 通信装置包括存储单元，行处理单元和列处理单元。 行处理单元重复执行行处理，以计算校验矩阵中的每列和每行的列处理LLR。 列处理单元针对每个列和校验矩阵的每一行计算行处理LLR，并且重复执行列处理，以在存储单元中存储行处理LLR的绝对值的最小值k。 行处理单元和列处理单元交替执行其处理。 行处理单元使用近似最小值执行计算，而列处理单元循环地更新每行的最小k值。