公开(公告)号：US20120169412A1

公开(公告)日：2012-07-05

申请号：US13341483

申请日：2011-12-30

申请人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

发明人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

IPC分类号： G05F3/08

CPC分类号： G06F1/26 ,  G06F1/3203 ,  H03K17/223

摘要： Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

摘要翻译： 常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。 供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。 示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

公开(公告)号：US20090080885A1

公开(公告)日：2009-03-26

申请号：US11915636

申请日：2005-05-27

申请人： Pronita Mehrotra ,  Dan Stevenson ,  Mark Cassada ,  Wayne Dettloff

发明人： Pronita Mehrotra ,  Dan Stevenson ,  Mark Cassada ,  Wayne Dettloff

IPC分类号： H04J14/02 ,  H04J3/16

CPC分类号： H04Q11/0066 ,  H04J14/0227 ,  H04Q2011/0064

摘要： An optical network scheduling device (10) including a plurality of schedulers (16) each corresponding to a respective channel in the optical burst switch network and configured to maintain a transmission schedule for the respective channel; and a controller (12) configured to receive a burst transmission request and to select at least one of the schedulers as a selected scheduler schedule a burst transmission.

摘要翻译： 一种光网络调度设备（10），包括多个调度器（16），每个调度器对应于所述光突发交换机网络中的相应信道，并且被配置为维持相应信道的传输调度; 以及控制器（12），被配置为接收突发传输请求并且选择所述调度器中的至少一个作为所选择的调度器调度突发传输。

公开(公告)号：US08618869B2

公开(公告)日：2013-12-31

申请号：US13341483

申请日：2011-12-30

申请人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

发明人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

IPC分类号： G05F1/10

CPC分类号： G06F1/26 ,  G06F1/3203 ,  H03K17/223

摘要： Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

摘要翻译： 常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。 供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。 示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

公开(公告)号：US20060016481A1

公开(公告)日：2006-01-26

申请号：US11188139

申请日：2005-07-22

申请人： Kevin Douglas ,  William Teach ,  Paul Gibson ,  Donald Harris ,  Scott Goodwin ,  David Dausch ,  Wayne Dettloff

发明人： Kevin Douglas ,  William Teach ,  Paul Gibson ,  Donald Harris ,  Scott Goodwin ,  David Dausch ,  Wayne Dettloff

IPC分类号： G05D7/06

CPC分类号： F16K99/0001 ,  F15C5/00 ,  F16K99/0007 ,  F16K99/0028 ,  F16K99/0051 ,  F16K2099/0074 ,  F16K2099/008 ,  G05D7/0694 ,  Y10T137/0491 ,  Y10T137/0497 ,  Y10T137/2213 ,  Y10T137/2224 ,  Y10T137/7761 ,  Y10T137/86558 ,  Y10T137/87169 ,  Y10T137/87217 ,  Y10T137/87225

摘要： A valve assembly may include a main housing and first and second electro-statically actuated valves. The main housing may define at least three chambers, with a first chamber configured to be coupled to a high pressure supply port, a second chamber configured to be coupled to an output port, and a third chamber configured to be coupled to a low pressure exhaust port. The first electro-statically actuated valve may be provided between the first and second chambers, and the first electro-statically actuated valve may allow or substantially block fluid communication between the first chamber and the second chamber responsive to a first electrical signal. The second electro-statically actuated valve may be provided between the second and third chambers, and the second electro-statically actuated valve may allow or substantially block fluid communication between the second chamber and the third chamber responsive to a second electrical signal. Related methods are also discussed.

摘要翻译： 阀组件可以包括主壳体和第一和第二静电致动阀。 主壳体可以限定至少三个室，其中第一室被配置为联接到高压供应端口，第二室被配置为联接到输出端口，第三室被配置为联接到低压排气 港口。 第一静电致动阀可以设置在第一和第二室之间，并且第一电动致动阀可以响应于第一电信号而允许或基本上阻挡第一室和第二室之间的流体连通。 第二电动致动阀可以设置在第二和第三室之间，并且第二电动致动阀可以响应于第二电信号而允许或基本上阻挡第二室和第三室之间的流体连通。 还讨论了相关方法。

公开(公告)号：US08498344B2

公开(公告)日：2013-07-30

申请号：US12999495

申请日：2009-06-18

申请人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

发明人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H04L25/49 ,  H04L25/4915

摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

摘要翻译： 数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。 设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。 可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。 检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。

公开(公告)号：US20110127990A1

公开(公告)日：2011-06-02

申请号：US12999495

申请日：2009-06-18

申请人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

发明人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

IPC分类号： G01R23/165

CPC分类号： H04L25/49 ,  H04L25/4915

摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

摘要翻译： 数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。 设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。 可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。 检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。