公开(公告)号：US07434112B2

公开(公告)日：2008-10-07

申请号：US11308571

申请日：2006-04-08

申请人： Kai Chen ,  Ru-Da Xu ,  Wei-Sheng Lin ,  Wen-Chih Hsu

发明人： Kai Chen ,  Ru-Da Xu ,  Wei-Sheng Lin ,  Wen-Chih Hsu

IPC分类号： G06F11/00

CPC分类号： G06F13/409

摘要： A system for verifying the validity of assembled PCI devices of a computer includes: a device database (2) for storing data of PCI devices being inserted in PCI slots of a computer; a slot database (3) for storing PCI slot data of the computer; a data checking module (1) for obtaining the computer's PCI device data and PCI slot data from the device database and the slot database, integrating the PCI device data and PCI slot data, generating configuration data of a PCI device, and determining whether the PCI device is assembled with validity. A method for verifying the validity of assembled PCI devices of a computer is also disclosed.

摘要翻译： 一种用于验证计算机组装的PCI设备的有效性的系统，包括：用于存储插入到计算机的PCI插槽中的PCI设备的数据的设备数据库（2） 用于存储计算机的PCI时隙数据的时隙数据库（3）; 数据检查模块（1），用于从设备数据库和时隙数据库获取计算机的PCI设备数据和PCI插槽数据，将PCI设备数据和PCI插槽数据进行集成，生成PCI设备的配置数据，以及确定PCI 设备组合有效。 还公开了一种用于验证计算机的组装的PCI设备的有效性的方法。

公开(公告)号：US20060242347A1

公开(公告)日：2006-10-26

申请号：US11308571

申请日：2006-04-08

申请人： Kai Chen ,  Ru-Da Xu ,  Wei-Sheng Lin ,  Wen-Chih Hsu

发明人： Kai Chen ,  Ru-Da Xu ,  Wei-Sheng Lin ,  Wen-Chih Hsu

IPC分类号： G06F13/00 ,  H05K7/10

CPC分类号： G06F13/409

摘要： A system for verifying the validity of assembled PCI devices of a computer includes: a device database (2) for storing data of PCI devices being inserted in PCI slots of a computer; a slot database (3) for storing PCI slot data of the computer; a data checking module (1) for obtaining the computer's PCI device data and PCI slot data from the device database and the slot database, integrating the PCI device data and PCI slot data, generating configuration data of a PCI device, and determining whether the PCI device is assembled with validity. A method for verifying the validity of assembled PCI devices of a computer is also disclosed.

摘要翻译： 一种用于验证计算机组装的PCI设备的有效性的系统，包括：用于存储插入到计算机的PCI插槽中的PCI设备的数据的设备数据库（2） 用于存储计算机的PCI时隙数据的时隙数据库（3）; 数据检查模块（1），用于从设备数据库和时隙数据库获取计算机的PCI设备数据和PCI插槽数据，将PCI设备数据和PCI插槽数据进行集成，生成PCI设备的配置数据，以及确定PCI 设备组合有效。 还公开了一种用于验证计算机的组装的PCI设备的有效性的方法。

公开(公告)号：US08426226B2

公开(公告)日：2013-04-23

申请号：US13342431

申请日：2012-01-03

申请人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

发明人： Jen-Inn Chyi ,  Geng-Yen Lee ,  Wei-Sheng Lin

IPC分类号： H01L21/00

CPC分类号： H01L27/15

摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.

摘要翻译： 一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。 由此，肖特基二极管经由金属层与LED电连接。 从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

公开(公告)号：US20130034919A1

公开(公告)日：2013-02-07

申请号：US13342431

申请日：2012-01-03

申请人： Jen-Inn CHYI ,  Geng-Yen Lee ,  Wei-Sheng Lin

发明人： Jen-Inn CHYI ,  Geng-Yen Lee ,  Wei-Sheng Lin

IPC分类号： H01L33/36

CPC分类号： H01L27/15

摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.

摘要翻译： 一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。 由此，肖特基二极管经由金属层与LED电连接。 从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

公开(公告)号：US07180161B2

公开(公告)日：2007-02-20

申请号：US11039432

申请日：2005-01-19

申请人： Lien-Chen Chiang ,  Wei-Sheng Lin

发明人： Lien-Chen Chiang ,  Wei-Sheng Lin

IPC分类号： H01L23/495 ,  H01L23/02 ,  H01L23/20 ,  H01L23/06

CPC分类号： H01L24/48 ,  H01L21/4825 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48664 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/78307 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85464 ,  H01L2224/85951 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/00012

摘要： A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.

摘要翻译： 提出了一种用于提高成型可靠性的引线框架和具有引线框架的半导体封装。 在引线框架的引线接合区域的接合层上形成至少一个压花结构，例如金属凸块或凹陷部分。 至少一个半导体芯片通过接合到接合层的接合线电连接到引线框架。 在用于制造密封剂以密封芯片，接合线和引线框架的一部分的模制过程中，压花结构使得结合层变得不均匀，从而增加了接合层和密封剂之间的接触面积和粘合力，因此 以防止接合线的裂纹，并提高电气性能和成型可靠性。

公开(公告)号：US20060006505A1

公开(公告)日：2006-01-12

申请号：US11039432

申请日：2005-01-19

申请人： Lien-Chen Chiang ,  Wei-Sheng Lin

发明人： Lien-Chen Chiang ,  Wei-Sheng Lin

IPC分类号： H01L23/495

CPC分类号： H01L24/48 ,  H01L21/4825 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48664 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/78307 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85464 ,  H01L2224/85951 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/00012

摘要： A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.

摘要翻译： 提出了一种用于提高成型可靠性的引线框架和具有引线框架的半导体封装。 在引线框架的引线接合区域的接合层上形成至少一个压花结构，例如金属凸块或凹陷部分。 至少一个半导体芯片通过接合到接合层的接合线电连接到引线框架。 在用于制造密封剂以密封芯片，接合线和引线框架的一部分的模制过程中，压花结构使得结合层变得不均匀，从而增加了接合层和密封剂之间的接触面积和粘合力，因此 以防止接合线的裂纹，并提高电气性能和成型可靠性。