公开(公告)号：US06746920B1

公开(公告)日：2004-06-08

申请号：US10337330

申请日：2003-01-07

申请人： Wen-Ying Wen ,  Jyh-Long Horng

发明人： Wen-Ying Wen ,  Jyh-Long Horng

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28114 ,  H01L21/28273

摘要： The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a semiconductor substrate to form a L-shaped poly spacer, which is so called the L-shaped floating gate. The respective inside portion of L-shaped floating gate is gibbous and to form a tip structure. Then, an isolating dielectric layer and a control gate are formed thereon. The control gate is covering the gibbous tip structure of the L-shaped floating gate to complete a flash memory device. The present invention is provided with a channel length, which is stably and easily controlled, and a tip structure for point discharging. Hence, the present invention can enhance the isolating effect between the control gate and the floating gate to achieve the purpose of repeating control the fabrication of the semiconductor devices.

摘要翻译： 本发明一般涉及提供具有L形浮动栅极的闪速存储器的制造方法。 本发明利用在半导体衬底的表面上的介电隔离层来形成L形的隔离层，这就是所谓的L形浮栅。 L形浮栅的各自内部是隆起并形成尖端结构。 然后，在其上形成隔离电介质层和控制栅极。 控制门覆盖L形浮动门的前端结构，完成闪存装置。 本发明提供一种稳定且易于控制的通道长度，以及用于点放电的尖端结构。 因此，本发明可以增强控制栅极和浮置栅极之间的隔离效应，以达到重复控制半导体器件的制造的目的。

公开(公告)号：US06624028B1

公开(公告)日：2003-09-23

申请号：US10086418

申请日：2002-03-04

申请人： Wen-Ying Wen

发明人： Wen-Ying Wen

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/2815 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

摘要： The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

摘要翻译： 本发明提供了一种诸如闪存单元的装置的制造方法，其用于制造作为浮动栅极的聚间隔物。 在本发明中，在半导体衬底的表面上依次形成氧化物，预定和图案化的第一电介质，第一多晶硅和第二电介质。 接下来，对第二电介质进行各向异性蚀刻，以在第一多晶硅的投射侧周围形成电介质间隔物。 然后用介电间隔物作为掩模蚀刻第一多晶硅。 随后，去除第一电介质。 因此完成了聚间隔物。 多隔板用作浮动栅极来完成闪存。 因此可以获得稳定性和容易控制的通道长度以及用于点放电的尖端，从而可以实现对半导体器件的制造的重复控制。

公开(公告)号：US06518110B2

公开(公告)日：2003-02-11

申请号：US09758310

申请日：2001-01-12

申请人： Wen Ying Wen

发明人： Wen Ying Wen

IPC分类号： H01L218238

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate. Thereby the present invention can not only achieve self-alignment to form the control gate and apply to high-integration memory cells with small areas, but also can release electrons from the floating gate to the control gate by the FN tunneling effect to effectively increase efficiency of erasing data and reliability of devices.

摘要翻译： 闪速存储器的存储单元结构及其制造方法技术领域本发明涉及闪速存储器的存储单元结构及其制造方法，更具体地，涉及具有环形浮动栅极的闪存。 本发明使用源极和浮置栅极之间的电容耦合在浮置栅极下的衬底中形成沟道。 热电子被注入到浮动栅极中，或者通过在浮置栅极的顶部上的注入点通过非导电的方式从浮置栅极释放到控制栅极。在所提出的存储单元中，浮动栅极被蚀刻以形成位于漏极 ，源和两个场氧化物。 互补电介质和控制栅极依次通过自对准的方式堆叠在浮动栅极和基板的未被浮动栅极覆盖的表面上。 在浮栅的顶部上形成未被多聚电介质的SiN膜覆盖的注入点。 因此，本发明不仅可以实现自对准以形成控制栅极并且应用于具有小面积的高积分存储器单元，而且还可以通过FN隧穿效应将电子从浮栅释放到控制栅极以有效地提高效率 擦除设备的数据和可靠性。

公开(公告)号：US5977598A

公开(公告)日：1999-11-02

申请号：US935869

申请日：1997-09-23

申请人： Chih-Ming Chen ,  Wen-Ying Wen ,  Chun Hung Peng

发明人： Chih-Ming Chen ,  Wen-Ying Wen ,  Chun Hung Peng

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/74 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： This invention discloses a memory cell that has a first polysilicon, which functions as a gate. The memory cell further includes a first TEOS oxide layer overlying the first polysilicon and a plurality of via-1 openings exposing the first polysilicon therein. The memory cell further includes a patterned second polysilicon layer overlying the first TEOS oxide layer and filling the via-1 openings thus contacting the gate wherein the patterned second polysilicon containing dopant ions for functioning as a connector for the memory cell. The memory cell further includes a second TEOS oxide layer overlying the connector includes a plurality of via-2 openings for exposing the connector therein. The memory cell further includes a silicide barrier layer disposed in the via-2 openings. And, The memory cell further includes a patterned third polysilicon layer overlying the second TEOS oxide layer and in contact with the silicide for contacting the connector thereunder wherein the patterned third polysilicon layer containing dopants therein to function as a load resistor for the memory cell.

摘要翻译： 本发明公开了一种存储单元，其具有用作栅极的第一多晶硅。 存储单元还包括覆盖第一多晶硅的第一TEOS氧化物层和暴露其中的第一多晶硅的多个通孔-1开口。 存储单元还包括覆盖在第一TEOS氧化物层上的图案化的第二多晶硅层，并且填充通孔1开口，从而接触栅极，其中所述图案化的第二多晶硅含有掺杂剂离子用作存储器单元的连接器。 所述存储单元还包括覆盖所述连接器的第二TEOS氧化物层，所述第二TEOS氧化物层包括用于将所述连接器暴露于其中的多个通孔-2开口。 存储单元还包括设置在通孔2开口中的硅化物阻挡层。 并且，存储单元还包括覆盖在第二TEOS氧化物层上且与硅化物接触的图案化的第三多晶硅层，用于接触其下的连接器，其中在其中包含掺杂剂的图案化的第三多晶硅层用作存储器单元的负载电阻器。

公开(公告)号：US06767792B1

公开(公告)日：2004-07-27

申请号：US10389944

申请日：2003-03-18

申请人： Wen-Ying Wen ,  Jyh-Long Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

发明人： Wen-Ying Wen ,  Jyh-Long Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

摘要翻译： 本发明一般涉及提供一种用于形成具有浮动栅极的可调节尖端结构的闪速存储器件的制造方法。 虽然本发明利用电介质间隔件来形成具有尖端结构的L形浮动栅极，但是本发明调节了覆盖在多晶硅层表面上的多晶硅层和电介质层的厚度以调节电介质的位置 间隔件，以改变L形浮栅的尖端结构的位置，并增强擦除闪存的控制能力，同时形成稳定且容易控制的通道长度，并且尖端结构用于点放电 。

公开(公告)号：US06500714B1

公开(公告)日：2002-12-31

申请号：US09607769

申请日：2000-06-30

申请人： Wen-Ying Wen

发明人： Wen-Ying Wen

IPC分类号： H01L218234

CPC分类号： H01L27/11226 ,  H01L27/112

摘要： In a traditional ROM semiconductor process, ROM codes are performed by ion implantation. Due to the limitations of ion implantation energy and threshold control, the implantation for program codes must be performed before forming an inter-layer oxide layer. Therefore, the required delivery time of the process becomes longer. The invention provide a method of manufacturing ROMs that can shorten delivery time by using only one mask to simultaneously form program codes and contact windows.

摘要翻译： 在传统的ROM半导体工艺中，通过离子注入执行ROM代码。 由于离子注入能量和阈值控制的限制，必须在形成层间氧化物层之前执行程序代码的注入。 因此，过程所需的交货时间变长。 本发明提供了一种制造ROM的方法，其可以通过仅使用一个掩模来同时形成程序代码和接触窗口来缩短传送时间。

公开(公告)号：US06649475B1

公开(公告)日：2003-11-18

申请号：US10158154

申请日：2002-05-31

申请人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

发明人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

摘要翻译： FLASH器件的结构包括形成在衬底上的第一介电层。 具有形成在第一电介质层上的间隔物轮廓的浮动栅极。 在浮动栅上形成介质隔离层用于隔离。 沿着浮动栅极和电介质间隔物的大致垂直表面形成第二电介质层，并且第二电介质层的横向部分在靠近浮动栅极的基板上横向延伸。 控制栅极形成在第二电介质层的横向延伸超过衬底的横向部分上。 控制栅极形成在第二介质层的侧面部分上。

公开(公告)号：US06187638B1

公开(公告)日：2001-02-13

申请号：US09205704

申请日：1998-12-04

申请人： Wen-Ying Wen

发明人： Wen-Ying Wen

IPC分类号： H01L218236

CPC分类号： H01L27/1126

摘要： A method is provided for manufacturing a memory cell with a increased threshold voltage accuracy. The memory cell has a substrate including a plurality of first conducting lines in a first direction and a plurality of second conducting lines in a second direction. The method includes the steps of forming a photoresist layer over the first and the second conducting lines, forming a window on the photoresist layer to expose a portion of the second conducting lines, thinning the portion of the second conducting lines in the windows, and doping impurities into the substrate between two of the first conducting lines to form the memory cell.

摘要翻译： 提供了一种用于制造具有增加的阈值电压精度的存储单元的方法。 存储单元具有包括沿第一方向的多条第一导线和在第二方向上的多条第二导线的基板。 该方法包括以下步骤：在第一和第二导电线上形成光致抗蚀剂层，在光致抗蚀剂层上形成窗口以暴露第二导电线的一部分，使窗口中的第二导电线的部分变薄，掺杂 在两条第一导线之间的衬底中的杂质形成存储单元。

公开(公告)号：US5956585A

公开(公告)日：1999-09-21

申请号：US803035

申请日：1997-02-19

申请人： Wen-Ying Wen

发明人： Wen-Ying Wen

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1104

摘要： A method of manufacturing a semiconductor cell comprises a step of anisotropically dry etching a polysilicon layer to form a polysilicon gate wherein an etching stop is formed on a buried contact region before the anisotropically dry etching step, the etching stop is preferably formed by salicide technology of titanium silicide.

摘要翻译： 制造半导体单元的方法包括：各向异性干蚀刻多晶硅层以形成多晶硅栅极的步骤，其中在各向异性干法蚀刻步骤之前在掩埋接触区域上形成蚀刻阻挡层，蚀刻停止层最好由硅化物技术形成 硅化钛

公开(公告)号：US06169008A

公开(公告)日：2001-01-02

申请号：US09166680

申请日：1998-10-05

申请人： Wen-Ying Wen ,  Chih-Ming Chen

发明人： Wen-Ying Wen ,  Chih-Ming Chen

IPC分类号： H01L2120

CPC分类号： H01L28/10 ,  H01L27/08

摘要： A high Q inductor and its forming method is disclosed. In this forming method, a semiconductor substrate is first provided with a trench formed thereon. The trench is defined by dry etching and formed to a depth of 3˜5 &mgr;m. A material having a higher resistivity than that of the semiconductor is then provided to fill the trench. The material can be formed by first depositing an epitaxy layer with a lower dopant concentration than that of the semiconductor substrate by several orders of magnitude on the semiconductor substrate, then etching back the epitaxy layer to expose the surface of the semiconductor substrate. Thereafter, a dielectric layer is formed on the semiconductor substrate and the trench, and an inductor winding is formed on the dielectric layer above the trench to form the high Q inductor.

摘要翻译： 公开了一种高Q电感器及其形成方法。 在这种形成方法中，半导体衬底首先设置有形成在其上的沟槽。 沟槽通过干蚀刻定义，形成深度为3〜5μm。 然后提供具有比半导体更高的电阻率的材料以填充沟槽。 可以通过首先在半导体衬底上沉积比半导体衬底的掺杂剂浓度低几个数量级的外延层，然后蚀刻外延层以暴露半导体衬底的表面来形成材料。 此后，在半导体衬底和沟槽上形成电介质层，并且在沟槽上方的电介质层上形成电感器绕组以形成高Q电感。