公开(公告)号：US06649475B1

公开(公告)日：2003-11-18

申请号：US10158154

申请日：2002-05-31

申请人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

发明人： Wen-Ying Wen ,  Jyhlong Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

摘要翻译： FLASH器件的结构包括形成在衬底上的第一介电层。 具有形成在第一电介质层上的间隔物轮廓的浮动栅极。 在浮动栅上形成介质隔离层用于隔离。 沿着浮动栅极和电介质间隔物的大致垂直表面形成第二电介质层，并且第二电介质层的横向部分在靠近浮动栅极的基板上横向延伸。 控制栅极形成在第二电介质层的横向延伸超过衬底的横向部分上。 控制栅极形成在第二介质层的侧面部分上。

公开(公告)号：US06767792B1

公开(公告)日：2004-07-27

申请号：US10389944

申请日：2003-03-18

申请人： Wen-Ying Wen ,  Jyh-Long Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

发明人： Wen-Ying Wen ,  Jyh-Long Horng ,  Erik S. Jeng ,  Bai-Jun Kuo ,  Chih-Hsueh Hung

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

摘要翻译： 本发明一般涉及提供一种用于形成具有浮动栅极的可调节尖端结构的闪速存储器件的制造方法。 虽然本发明利用电介质间隔件来形成具有尖端结构的L形浮动栅极，但是本发明调节了覆盖在多晶硅层表面上的多晶硅层和电介质层的厚度以调节电介质的位置 间隔件，以改变L形浮栅的尖端结构的位置，并增强擦除闪存的控制能力，同时形成稳定且容易控制的通道长度，并且尖端结构用于点放电 。

公开(公告)号：US07777267B2

公开(公告)日：2010-08-17

申请号：US11969119

申请日：2008-01-03

申请人： Erik S Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik S Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅极电介质包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在去除最上层的材料之后重建一个新的顶部材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。

公开(公告)号：US20080150048A1

公开(公告)日：2008-06-26

申请号：US11969119

申请日：2008-01-03

申请人： Erik S. Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik S. Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of4terial. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅极电介质包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在删除最上层的四层后重建一个新的顶层材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。

公开(公告)号：US20050156228A1

公开(公告)日：2005-07-21

申请号：US10758132

申请日：2004-01-16

申请人： Erik Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L29/40117 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅介质层包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在去除最上层的材料之后重建一个新的顶部材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。