利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

4 条记录 (耗时 0.01 秒)

    FET Circuit for converting TTL to FET logic levels
    1.
    发明授权
    FET Circuit for converting TTL to FET logic levels 失效
    FET电路，用于将TTL转换为FET逻辑电平

    公开(公告)号：US4406956A

    公开(公告)日：1983-09-27

    申请号：US177298

    申请日：1980-08-11

    申请人： Rainer Clemen ,  Walter Fischer ,  Werner O. Haug

    发明人： Rainer Clemen ,  Walter Fischer ,  Werner O. Haug

    IPC分类号： H03K5/02 ,  H03K19/0185 ,  H03K19/092 ,  H03K19/094

    CPC分类号： H03K19/018507

    摘要： This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

    摘要翻译： 本发明涉及用于将双极晶体管逻辑电平转换为场效应晶体管逻辑电平的场效应晶体管电平转换器。 第一和第二场效应晶体管的源极和栅极共同连接。 双极性输入信号在公共源极连接处被接收，而栅电极接收等于阈值电压VT加上双极性输入逻辑的最低可能的高二进制电平的固定参考电位。 第一场效应晶体管的漏电极连接到电平转换器的输出端和源极跟随器晶体管的源电极。 第二晶体管的漏电极连接到负载器件和源极跟随器晶体管的栅极，其漏极连接到VH。 这种布置在第一输出端产生响应于0.8至2.0伏范围内的输入信号的大约0至7伏特的电位摆动。

    Integrated circuit package
    2.
    发明授权
    Integrated circuit package 失效
    集成电路封装

    公开(公告)号：US5162264A

    公开(公告)日：1992-11-10

    申请号：US696675

    申请日：1991-05-07

    申请人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

    发明人： Werner O. Haug ,  Erich Klink ,  Karl E. Kroll ,  Thomas Ludwig ,  Helmut Schettler ,  Rainer Stahl ,  Otto M. Wagner

    IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L23/64

    CPC分类号： H01L23/642 ,  H01L23/147 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/3011 ,  Y10S257/916 ,  Y10S438/901

    摘要： Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.At least one active integrated circuit chip (1) is mounted and electrically connected to the passive semiconductor interconnection carrier (2).

    摘要翻译： 集成电路封装，包括电源分配布线和芯片互连信号布线，两者均形成在其中实现电源去耦电容器的无源半导体互连载体（2）的顶表面上。 在第二导电类型的所述载体的表面中提供第一导电类型的间隔阱（4）。 电源分配布线包括在第一布线层（WL1）内的第一和第二导线（5,6）。 所述第一导线（5）以欧姆接触关系沉积在所述阱（4）的表面区域上，并且所述第二导线（6）沉积在所述孔（4）之间的所述载体（2）的表面区域上， 在欧洲的联系关系。 所述第一和第二导线分别连接到电源的第一和第二端子，使得所述阱（4）和嵌入所述阱的载体材料（2）之间的结电容形成所述去耦电容器。 至少一个有源集成电路芯片（1）被安装并电连接到无源半导体互连载体（2）。