公开(公告)号：US08264043B1

公开(公告)日：2012-09-11

申请号：US11411064

申请日：2006-04-25

申请人： Sanjay Rekhi ,  Nagendra Cherukupalli ,  Paul D. Keswick

发明人： Sanjay Rekhi ,  Nagendra Cherukupalli ,  Paul D. Keswick

IPC分类号： H01L23/60

CPC分类号： H01L27/0255 ,  H01L27/0266 ,  Y10S438/901

摘要： In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

摘要翻译： 在一个实施例中，第一晶体管被配置为在金属化处理期间接通以在互连线上排放累积电荷。 这有利地保护耦合到互连线的第二晶体管免受电荷积聚。 第一晶体管的栅极可以通过耦合电容耦合到互连线。 第一晶体管的栅极可以在金属化过程期间保持浮置，并且随后在最高金属水平处耦合到地。 金属化工艺可以是例如物理气相沉积。

公开(公告)号：US07309875B2

公开(公告)日：2007-12-18

申请号：US10995809

申请日：2004-11-22

申请人： Douglas A. Ohlberg

发明人： Douglas A. Ohlberg

IPC分类号： G11C11/00 ,  H01L51/10

CPC分类号： H01L51/0595 ,  B82Y10/00 ,  B82Y30/00 ,  G11C2213/77 ,  H01L27/285 ,  Y10S438/901 ,  Y10S438/962 ,  Y10S977/83 ,  Y10S977/943

摘要： A molecular device is provided. The molecular device comprises a junction formed by a pair of crossed electrodes where a first electrode is crossed by a second electrode at a non-zero angle and at least one connector species including at least one switchable moiety and connecting the pair of crossed electrode in the junction. The junction has a functional dimension ranging in size from microns to nanometers. The molecular device further includes a buffer layer comprising nanocrystals interposed between the connector species and the second electrode.

摘要翻译： 提供分子装置。 分子器件包括由一对交叉电极形成的结，其中第一电极以非零角度被第二电极交叉，并且至少一个连接器种类包括至少一个可切换部分，并将该对交叉电极连接在 交界处 结的功能尺寸范围从微米到纳米。 分子装置还包括缓冲层，该缓冲层包含介于连接器种类和第二电极之间的纳米晶体。

公开(公告)号：US20020045358A1

公开(公告)日：2002-04-18

申请号：US09912558

申请日：2001-07-26

发明人： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

IPC分类号： H01L021/31 ,  H01L021/469

CPC分类号： H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

摘要： A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

摘要翻译： 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US5843829A

公开(公告)日：1998-12-01

申请号：US559813

申请日：1995-11-17

申请人： Masaki Kuramae ,  Fumitake Mieno

发明人： Masaki Kuramae ,  Fumitake Mieno

IPC分类号： C23C16/52 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/2022 ,  H01L28/84 ,  H01L28/87 ,  Y10S438/901

摘要： A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在衬底上沉积非晶硅层，并通过用氧化气体处理非晶硅层的表面，在非晶硅层的表面上形成氧化膜。 形成步骤在非晶硅层结晶之前发生。

公开(公告)号：US5345105A

公开(公告)日：1994-09-06

申请号：US103362

申请日：1993-08-02

申请人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

发明人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

IPC分类号： H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L23/34 ,  H01L25/04

CPC分类号： H01L23/585 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  Y10S438/901

摘要： A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

摘要翻译： 一种屏蔽结构（10）及其形成方法。 屏蔽结构（10）具有基板（12）。 第一介电层（14）覆盖在基板（12）上。 形成覆盖在电介质层（14）上的导电层（16）被图案化，并被蚀刻以与导电层（16）形成电隔离的导电区域。 电绝缘的导电区域具有侧壁，并且导电层（16）的蚀刻暴露介电层（14）的部分。 电介质层（14）的暴露部分被蚀刻以形成电介质层（14）的沟槽部分。 形成第二介电层（18），覆盖电隔离的导电区域（包括侧壁）并覆盖沟槽部分以形成分离电隔离导电区域的凹陷区域。 屏蔽导电层（20）形成在覆盖介电层（18）上并且至少部分地填充凹陷区域以将电隔离的导电区域彼此隔离。

公开(公告)号：US5338691A

公开(公告)日：1994-08-16

申请号：US65567

申请日：1993-05-21

申请人： Yoshinari Enomoto ,  Yoshio Tsuruta

发明人： Yoshinari Enomoto ,  Yoshio Tsuruta

IPC分类号： H01L27/144 ,  H01L31/0288 ,  H01L31/0352 ,  H01L31/18

CPC分类号： H01L31/0288 ,  H01L27/1443 ,  H01L27/14689 ,  H01L31/03529 ,  H01L31/1804 ,  Y02E10/547 ,  Y10S438/901

摘要： The present invention discloses a light-receiving element, and method for making same, for a charge storage light sensor having a first semiconductor later of a first conductive type with an element isolation region disposed thereon. The element isolation regions are formed to produce tilted edges embedded within the first semiconductor layer and to also produce an embedded region of a second conductive type. The embedded region is effective to collect the photoelectric current resulting from light exposure to the first semiconductor layer regions upon the application of a reverse bias potential to the embedded region.

摘要翻译： 本发明公开了一种用于具有第一半导体的电荷存储光传感器的光接收元件及其制造方法，所述第一半导体具有设置在其上的元件隔离区域的第一导电类型。 形成元件隔离区域以产生嵌入第一半导体层内的倾斜边缘并且还产生第二导电类型的嵌入区域。 当对嵌入区域施加反向偏置电位时，嵌入区域有效地收集由于对第一半导体层区域的曝光而产生的光电流。

公开(公告)号：US5262353A

公开(公告)日：1993-11-16

申请号：US829837

申请日：1992-02-03

申请人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

发明人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

IPC分类号： H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L23/585 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  Y10S438/901

摘要： A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

摘要翻译： 一种屏蔽结构（10）及其形成方法。 屏蔽结构（10）具有基板（12）。 第一介电层（14）覆盖在基板（12）上。 形成覆盖在电介质层（14）上的导电层（16）被图案化，并被蚀刻以与导电层（16）形成电隔离的导电区域。 电绝缘的导电区域具有侧壁，并且导电层（16）的蚀刻暴露介电层（14）的部分。 电介质层（14）的暴露部分被蚀刻以形成电介质层（14）的沟槽部分。 形成第二介电层（18），覆盖电隔离的导电区域（包括侧壁）并覆盖沟槽部分以形成分离电隔离导电区域的凹陷区域。 屏蔽导电层（20）形成在覆盖介电层（18）上并且至少部分地填充凹陷区域以将电隔离的导电区域彼此隔离。

公开(公告)号：US5053352A

公开(公告)日：1991-10-01

申请号：US447849

申请日：1989-12-08

申请人： Reinhold Kaiser

发明人： Reinhold Kaiser

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/93

CPC分类号： H01L29/93 ,  Y10S257/926 ,  Y10S438/901

摘要： In a method of forming an integrated circuit array having a capacitance formed by a pn-junction and separated from other components by a pn-junction, semiconductor areas are provided which connect that zone of the two semiconductor zones forming the pn-junction of the capacitance that extends deeper into the semiconductor element than the other of the two semiconductor zones forming the pn-junction of the capacitance electrically to that zone of the two semiconductor zones forming the separating pn-junction that faces away from the capacitance.

公开(公告)号：US3769105A

公开(公告)日：1973-10-30

申请号：US3769105D

申请日：1971-04-12

申请人： IBM

发明人： CHEN C ,  DHAKA V ,  KROLIKOWSKI W

IPC分类号： H01L27/07 ,  H01L7/36 ,  H01L19/00

CPC分类号： H01L27/0794 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S438/901

摘要： An integrated circuit and process for making it wherein a decoupling capacitor is provided beneath devices in the surface of the integrated circuit by the formation of a first epitaxial layer between an N substrate having a P zone diffused therein and an N device-containing epitaxial layer. A P channel diffusion to the P zone formed in the substrate will serve as a damping resistor in combination with the coupling capacitor. The process for forming such a decoupling capacitor in an integrated circuit comprises, inter alia, diffusing P impurities into the substrate to form a large junction which will subsequently function as a decoupling capacitor. A first intrinsic, P or N epitaxial layer is then grown on the semiconductor substrate. Subsequently, an N epitaxial layer is grown on the first epitaxial layer. A P channel is then driven through the N epitaxial layer and the first epitaxial layer to contact the P diffused zone which serves as the decoupling capacitor. This P channel diffusion will serve as a damping resistor in combination with the decoupling capacitor. Device diffusion, i.e., transistors, resistors, etc., will take place into the N epitaxial layer, and during growth of the epitaxial layers the P zone will significantly outdiffuse into the first epitaxial layer. Appropriate channels, isolations and contacts are also provided.

摘要翻译： 一种用于制造其的集成电路和工艺，其中在集成电路的表面中的器件下方提供去耦电容器，该第一外延层在扩散在其中的P +区之间形成第一外延层，N + 含有器件的外延层。 在衬底中形成的P +区的P +沟道扩散将用作与耦合电容器组合的阻尼电阻器。 在集成电路中形成这种去耦电容器的过程尤其包括将P +杂质扩散到衬底中以形成随后用作去耦电容器的大结。 然后在半导体衬底上生长第一固有的P +或N - 外延层。 随后，在第一外延层上生长N +外延层。 然后通过N +外延层和第一外延层驱动P +沟道以接触用作去耦电容器的P +扩散区。 该P +通道扩散将与去耦电容器一起用作阻尼电阻器。 器件扩散，即晶体管，电阻器等将发生到N +外延层中，并且在外延层生长期间，P +区将显着地超出第一外延层的扩散。 还提供了适当的通道，隔离和触点。

公开(公告)号：US3560277A

公开(公告)日：1971-02-02

申请号：US3560277D

申请日：1968-01-15

申请人： IBM

发明人： LLOYD ROBERT H F ,  DAVIS STANLEY P ,  MYERS CHARLES FRANK

IPC分类号： H01L21/8222 ,  H01L27/02 ,  H01L7/36

CPC分类号： H01L21/8222 ,  H01L27/0229 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S438/901

摘要： A PROCESS FOR MAKING SEMICONDUCTOR BODIES, SAID BODIES HAVING POWER CONNECTIONS AND DECOUPLING MEANS INTERNAL THERETO, SAID CONNECTIONS CONPRISING DIFFUSED LOW RESISTANCE SEMICONDUCTOR REGIONS, WHEREIN SAID PROCESS COMPRISES THE STEPS OF FORMING THE LOW RESISTANCE REGIONS AND THE DECOUPLING MEANS BY A SERIES OF DIFFUSIONS INCLUDING CONTROLLED OUT-DIFFUSIONS.