公开(公告)号：US20060006166A1

公开(公告)日：2006-01-12

申请号：US10884933

申请日：2004-07-06

申请人： Howard Chen ,  William Ferrante ,  Louis Hsu ,  Carl Radens

发明人： Howard Chen ,  William Ferrante ,  Louis Hsu ,  Carl Radens

IPC分类号： H05B1/02 ,  H05B3/00

CPC分类号： G05D23/20 ,  G05D23/1931 ,  Y10T307/469

摘要： An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

摘要翻译： 片上温度控制系统包括监测芯片温度的温度传感器和检查温度是否在可接受范围内的滞后比较器。 如果温度超出范围，参考调节电路响应于迟滞比较器来调节片上电压以局部地调节局部电源电压来控制温度。

公开(公告)号：US20070113134A1

公开(公告)日：2007-05-17

申请号：US11163527

申请日：2005-10-21

申请人： William Ferrante ,  John Cassels ,  Stephen Wu

发明人： William Ferrante ,  John Cassels ,  Stephen Wu

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/31935 ,  G11C29/56008 ,  G11C2029/5604

摘要： Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array is disclosed. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data array is organized according to a translation table, which describes the locations of data for tests and criteria for data to be analyzed within the data array. Numerous other data arrangements such as a coordinate file listing a pre-defined maximum number of fail points, or a chip report including fail points by chip may also be generated. The data array reports all test data in a more easily generated and stored form, and may be converted to an image. A data analysis method for analyzing data using the data array is also disclosed.

摘要翻译： 公开了使用数据阵列从阵列结构的多个测试中报告和/或分析测试数据。 一种方法包括获得测试数据，并将测试数据报告在数据阵列中，该数据阵列包括表示不同测试的至少两个部分。 存储在数据阵列中的数据根据​​翻译表进行组织，该转换表描述了要在数据阵列中分析的数据的测试数据和标准的位置。 也可以生成诸如列出预定义的最大失败点数的坐标文件或包括芯片故障点的芯片报告的许多其他数据布置。 数据阵列以更容易生成和存储的形式报告所有测试数据，并可将其转换为图像。 还公开了一种用于使用数据阵列分析数据的数据分析方法。

公开(公告)号：US20050151213A1

公开(公告)日：2005-07-14

申请号：US10707746

申请日：2004-01-08

申请人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L31/058

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。