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1.发明授权Process and apparatus for interrupting and restarting sequential list-processing operations 失效用于中断和重新启动顺序列表处理操作的过程和设备
公开(公告)号：US4429360A
公开(公告)日：1984-01-31
申请号：US201880
申请日：1980-10-29
CPC分类号： G06F9/461
摘要： A method and apparatus are provided to enable interruption of list processing operations in a computer system and to enable restart from the point of interruption. A mechanism, at a predetermined point of the list processing operation, operates to recognize occurrences of interrupting events. If any such events are present, a mechanism saves the status of the list processing operation, saves the identification of the task associated with instruction executing the list processing operation and locks the list or queue. After the interrupt is handled, a mechanism restores status, and unlocks the list or queue only when the identified task is active again and the instruction which had been executing the list processing operation is again executing.
摘要翻译： 提供了一种方法和装置，以使中断计算机系统中的列表处理操作，并且能够从中断点启动重新启动。 在列表处理操作的预定点处的机制用于识别中断事件的发生。 如果存在任何这样的事件，则机制保存列表处理操作的状态，保存与执行列表处理操作的指令相关联的任务的标识，并锁定列表或队列。 处理中断后，机制恢复状态，只有当所识别的任务再次被激活并且执行列表处理操作的指令再次执行时，才能解锁列表或队列。
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公开(公告)号：US4262330A
公开(公告)日：1981-04-14
申请号：US954069
申请日：1978-10-23
CPC分类号： G06F9/3017 , G06F9/268 , G06F9/30145 , G06F9/30181
摘要： A control system for a computer includes a control store (30) for storing end op, I-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next microinstruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to I-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to I-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (3) to being E-phase.
摘要翻译： 一种用于计算机的控制系统包括用于存储结束操作，I-1，I-2和返回字的控制存储器（30）。 微指令解码和控制单元（170）响应终端op词来初始化和个性化计算机组件以便于后续执行高级指令。 控制单元（170）结合下一个地址逻辑（162），响应于高电平指令选择要执行的下一个微指令。 控制单元（170）和逻辑（162）响应I-1个字来个性化计算机并选择微指令以开始高电平指令的E相。 响应于I-2控制字，控制单元（170）和逻辑（162）在控制存储器（30）中选择操作数获取程序，并将第一E相地址写入本地存储器（138）。 返回字从本地存储器（138）门控第一个E相地址，以选择控制存储器（3）中的微指令为E相。
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公开(公告)号：US4286322A
公开(公告)日：1981-08-25
申请号：US54508
申请日：1979-07-03
CPC分类号： G06F9/4881 , G06F9/3009 , G06F9/3851
摘要： Improved task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.
摘要翻译： 改进的用于计算机系统的任务处理装置，其中任务分派器在指令控制下选择性地可操作以执行任务队列选择，并且其中任务间通信机制可以将任务调度元素（TDE）返回到非主要任务调度队列（TDQ），作为 以及主要的TDQ。 每当TDE返回到主要的TDQ时，任务调度员都将进行先发制人的任务切换。 此外，如果当前非主要TDQ上没有任务调度元素，则任务调度员切换到从主要TDQ分派TDE。
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公开(公告)号：US4241396A
公开(公告)日：1980-12-23
申请号：US953666
申请日：1978-10-23
CPC分类号： G06F12/1425
摘要： Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction.Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.
摘要翻译： 提供了标签指针处理装置，用于在计算机系统中实现，其中为主存储器中的每个字提供标签位。 本发明提供了在同一存储空间内的数据和指针的混合，并提供了检查和验证指针的有效性而不影响其他指令的性能或操作的能力。 标签指令只能在主存储器中设置标签位置ON; 所有其他指令存储数据并将相应的标记位设置为OFF。 因此，如果通过这些数据处理指令之一无意中修改了指针，则当指针由加载和验证标签指令使用时，检测到指针未标记的事实，并且指针中的值被视为无效。 加载，存储，设置，移动，提取和插入标签的指令由标记的指针处理装置实现。 加载和验证标签指令检查指针的有效性，如果有效，将指针加载到指定的通用寄存器中。 存储和设置标签指令将指定的通用寄存器中的值存储到主存储器中，并将关联的标签位置ON。 移动和设置标签指令将单词从主存储器中的一个位置移动到主存储器中的另一个位置或相同位置，并将关联的标签位置ON。 移动字符和标签指令将一个字和相关联的标签位从一个存储位置移动到另一个存储位置。 提取标签指令从主存储器中的操作数获取每个字，提取标签位，将标记位压缩为每个四字的一个标记位，并将标记位存储在主存储中作为数据。 插入标签指令将存储在主存储器中的标签位取为数据，将标记位扩展为每个字的一个标记位，并将其插入主存储中操作数的每个关联字。
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公开(公告)号：US4177513A
公开(公告)日：1979-12-04
申请号：US813901
申请日：1977-07-08
CPC分类号： G06F9/4881 , G06F9/546
摘要： Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms. The active task becomes inactive waiting when a receive message or receive count is not satisfied. An inactive dispatchable task becomes the active task when it becomes the highest priority enqueued TDE on the TDQ by the receive message or receive count mechanisms. An inactive waiting task becomes either the active task or an inactive dispatchable task after being enqueued on the TDQ by the send message or send count mechanisms, depending upon whether it is the highest or other than the highest priority TDE on the TDQ.
摘要翻译： 计算机系统中的任务处理装置被构造为对于系统控制任务，用户任务和I / O任务是共同的。 虽然任务处理设备包含任务优先级结构，但所有任务都以相同的方式进行处理，并且I / O任务没有固定的中断级别。 有N个优先级，N是可变的。 每个任务是一个功能请求的服务器。 任务调度元素（TDE）以任务调度队列（TDQ）的优先级顺序排队。 任务调度员可以在TDQ上发送最高优先级的TDE（如果有的话），并执行任务切换。 通过发送消息，发送计数，接收消息和接收计数机制完成任务间通信，并与任务同步相结合。 任务同步是通过在TDQ上排队和排队TDE实现的。 当通过发送消息或发送计数机制在TDQ上排队更高优先级的TDE时，活动任务变为不可分派。 当接收消息或接收计数不满足时，活动任务变为无效等待。 当通过接收消息或接收计数机制成为TDQ上的最高优先级入队TDE时，不活动的可分派任务成为主动任务。 一个不活动的等待任务在TDQ上被发送消息排入队列之后成为活动任务或不可分派的任务，或者发送计数机制，这取决于它是否是TDQ上最高优先级TDE或TDE以外的最高优先级TDE。
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公开(公告)号：US4266272A
公开(公告)日：1981-05-05
申请号：US950898
申请日：1978-10-12
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1076 , G06F11/28
摘要： Control circuitry is provided for controlling the generation of a block check word simultaneously with the writing of control words into a transient area of a writeable control storage. The control circuitry in response to a write control storage instruction generates control signals for controlling existing central processing unit (CPU) hardware to effect generation of the block check word while a control word is being written into the transient area of control storage. Microinstructions in the resident area for performing the overlay force selection of a local storage register which has been initialized. The operand from the local storage register is applied to the ALU together with the word which is also being written into control storage. The ALU is forced to perform an exclusive OR operation and the result is returned to the selected LSR. In this manner a block check word is dynamically calculated word by word as each word is written into control storage. When all the control words have been loaded into control storage, a pre-calculated block check word is retrieved from main storage and compared with the calculated block check word. A miscompare indicates that the group of control words written into control storage had been modified when resident in main storage.
摘要翻译： 提供控制电路，用于在将控制字写入可写控制存储器的暂存区域的同时控制块校验字的产生。 响应于写入控制存储指令的控制电路产生用于控制现有中央处理单元（CPU）硬件的控制信号，以在控制字被写入控制存储器的暂时区域的同时产生块检查字。 驻留区域中的微指令用于执行已初始化的本地存储寄存器的叠加力选择。 来自本地存储寄存器的操作数与被写入控制存储器的字一起被应用于ALU。 ALU被强制执行异或运算，结果返回到选定的LSR。 以这种方式，每个字被写入控制存储器中逐个地动态地计算块检查字。 当所有控制字已经被加载到控制存储器中时，从主存储器检索预先计算的块检查字，并与计算的块校验字进行比较。 错误的比较表明，当存储在主存储中时，写入控制存储的控制字组被修改。
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公开(公告)号：US4298927A
公开(公告)日：1981-11-03
申请号：US954068
申请日：1978-10-23
CPC分类号： G06F9/3814 , G06F9/3802
摘要： A digital computer system including a computation unit (14), a main store (12), a virtual address translator (10), a microinstruction control unit (170) and an instruction code prefetch circuit (212). User instruction codes are stored sequentially in the main store (12) which is accessed for read and write operations by the virtual address translator (10). The instruction code prefetch circuit (212) retrieves the user instruction codes from the main store (12) and holds the instruction codes in a register (16, 18). The instruction codes are transferred from the register (16, 18) to the computation unit (14) in sequential order of use. The microinstruction control unit (170) produces selected microinstructions which are executed by the computation unit (14) to accomplish the operations specified by the user instructions. Designated microinstructions include commands which activate the instruction code prefetch circuit (212) to retrieve the succeeding user instruction codes from the main store (12).
摘要翻译： 一种数字计算机系统，包括计算单元（14），主存储器（12），虚拟地址转换器（10），微指令控制单元（170）和指令代码预取电路（212）。 用户指令码顺序存储在由虚拟地址转换器（10）读取和写入操作的主存储器（12）中。 指令代码预取电路（212）从主存储器（12）检索用户指令代码，并将指令代码保存在寄存器（16,18）中。 指令码按照使用顺序从寄存器（16,18）传送到计算单元（14）。 微指令控制单元（170）产生由计算单元（14）执行以完成由用户指令指定的操作的所选微指令。 指定的微指令包括激活指令代码预取电路（212）以从主存储器（12）检索后续用户指令代码的命令。
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