公开(公告)号：US06275442B1

公开(公告)日：2001-08-14

申请号：US09572042

申请日：2000-05-16

申请人： J. Michael Hill ,  Jonathan E. Lachman ,  William J. Queen

发明人： J. Michael Hill ,  Jonathan E. Lachman ,  William J. Queen

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C29/02

摘要： A decoder circuit in a memory system accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, such as word lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each latch output is connected to an AND gate input, and each AND gate output is one of the plurality of decode lines. In another sense, the decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs. The outputs of each non-final stage is an input to a subsequent stage. The set of latches are connected to the outputs of a particular non-final stage. A method for using the decoder processes a set of input signals, whereby a set of processed signals are generated. The method latches the processed signals. The latched signals are intermediate signals in a decoding operation, and the method further processes the intermediate signals so as to complete the decoding operation.

摘要翻译： 存储器系统中的解码器电路接收时钟信号和多个地址线作为输入，并且产生诸如字线的多条解码线作为输出。 解码器电路包括多个预解码电路，多个锁存器和多个与门。 每个预解码电路连接到时钟信号和多个地址线的子集及其补码的唯一组合。 每个预解码电路产生响应于多个地址线的相应子集的唯一状态设置的输出。 每个锁存器输入连接到多个预解码电路中的相应一个的输出端。 每个锁存器输出连接到与门输入，每个与门输出是多条译码线之一。 在另一个意义上，解码器包括解码逻辑和一组锁存器的一个或多个阶段。 解码逻辑的第一阶段接受解码器输入。 每个非最后阶段的输出是后续阶段的输入。 锁存器组连接到特定非最终级的输出端。 一种使用解码器的方法处理一组输入信号，从而产生一组处理的信号。 该方法锁存已处理的信号。 锁存信号是解码操作中的中间信号，并且该方法进一步处理中间信号以完成解码操作。

公开(公告)号：US5692026A

公开(公告)日：1997-11-25

申请号：US657732

申请日：1996-05-31

申请人： Kenneth Koch, II ,  William J. Queen

发明人： Kenneth Koch, II ,  William J. Queen

IPC分类号： G11C19/00 ,  H03K23/54

CPC分类号： H03K23/54 ,  G11C19/00

摘要： A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clock input and a shift input. The data output of each cell is coupled to the data input of an adjacent cell. At least one pass-AND gate is provided for each cell. The pass-AND gate has a switching input and a switched input. The switching input operates to toggle the input capacitance of the switched input between a larger and a smaller value. The logical OR of the data input and data output of each cell is used to drive the switching input of the associated pass-AND gates for that cell. The switched input of the pass-AND gate is adapted to be coupled to the clock (or shift) signal, and the output of the pass-AND gate is coupled to the clock (or shift) input of the data cell. When two such pass-AND gates are provided for each cell, one may be used for the clock signal, and the other for the shift signal. In this manner, only those cells of the shift register, circular pointer or ring counter whose outputs are asserted, or will become asserted during the next shift operation, will present a larger capacitance to the clock and shift signals. All of the other cells will present a smaller capacitance to the clock and shift signals.

摘要翻译： 移位寄存器，圆形指针或环形计数器在时钟上呈现降低的电容性负载，并且用于控制它的移位信号。 使用一个或多个增强数据单元构造该设备。 每个数据单元具有数据输入，数据输出，时钟输入和移位输入。 每个单元的数据输出耦合到相邻单元的数据输入。 为每个单元提供至少一个通过与门。 通门AND门具有开关输入和开关输入。 开关输入用于切换开关输入的输入电容在较大和较小值之间。 每个单元的数据输入和数据输出的逻辑“或”用于驱动该单元的关联的通过与门的切换输入。 通过与门的开关输入适于耦合到时钟（或移位）信号，并且通过与门的输出耦合到数据单元的时钟（或移位）输入。 当为每个单元提供两个这样的通过AND门时，可以使用时钟信号，另一个用于移位信号。 以这种方式，只有移位寄存器的这些单元，其输出被置位的环形指针或环形计数器，或者将在下一个移位操作期间被置为有效，才会给时钟和移位信号带来更大的电容。 所有其他单元将对时钟和移位信号呈现较小的电容。

公开(公告)号：US5831990A

公开(公告)日：1998-11-03

申请号：US667037

申请日：1996-06-19

申请人： William J. Queen ,  Russell W. Mason

发明人： William J. Queen ,  Russell W. Mason

IPC分类号： G01R31/317 ,  G06F11/00

CPC分类号： G01R31/31701

摘要： A dynamic logic circuit having additional test circuitry and control, enabling the dynamic logic gate to operate normally during testing or alternatively to force the dynamic logic gate output to a known state during testing to provide a known input for downstream logic. With the additional test circuitry, there is no need for input test signal sequences to propagate logical test vectors to tested nodes. The dynamic logic circuit includes a storage node that is precharged during a precharge cycle and logic circuitry that may discharge the storage node during an evaluation cycle, depending on logic inputs. The logic circuitry discharges through a clock transistor. Additional test circuitry is added to discharge the storage node during the evaluation cycle, in response to a test control signal and a test state signal. When the dynamic logic gate is operating normally during testing, the test circuitry is disabled. When the gate output is to forced into a known state, the clock transistor is disabled, disabling the logic circuitry, and the test circuitry discharges the storage node, depending on the test state signal.

摘要翻译： 具有附加测试电路和控制的动态逻辑电路，使得动态逻辑门能够在测试期间正常运行，或者替代地在测试期间将动态逻辑门输出强制为已知状态，以向下游逻辑提供已知输入。 使用附加的测试电路，不需要输入测试信号序列来将逻辑测试向量传播到被测试的节点。 动态逻辑电路包括在预充电周期期间预充电的存储节点和根据逻辑输入可以在评估周期期间释放存储节点的逻辑电路。 逻辑电路通过时钟晶体管放电。 响应于测试控制信号和测试状态信号，添加额外的测试电路以在评估周期期间对存储节点进行放电。 当测试期间动态逻辑门正常工作时，测试电路被禁用。 当栅极输出被强制进入已知状态时，时钟晶体管被禁止，禁用逻辑电路，并且测试电路根据测试状态信号放电存储节点。