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1.发明授权Apparatus for reducing capacitive loading of clock and shift signals by shifting register-based devices 失效用于通过移位基于寄存器的器件来减少时钟和移位信号的电容负载的装置
公开(公告)号：US5692026A
公开(公告)日：1997-11-25
申请号：US657732
申请日：1996-05-31
申请人： Kenneth Koch, II , William J. Queen
发明人： Kenneth Koch, II , William J. Queen
摘要： A shift register, circular pointer or ring counter presents a reduced capacitive load on the clock and shift signals used to control it. The device is constructed using one or more enhanced data cells. Each data cell has a data input, a data output, a clock input and a shift input. The data output of each cell is coupled to the data input of an adjacent cell. At least one pass-AND gate is provided for each cell. The pass-AND gate has a switching input and a switched input. The switching input operates to toggle the input capacitance of the switched input between a larger and a smaller value. The logical OR of the data input and data output of each cell is used to drive the switching input of the associated pass-AND gates for that cell. The switched input of the pass-AND gate is adapted to be coupled to the clock (or shift) signal, and the output of the pass-AND gate is coupled to the clock (or shift) input of the data cell. When two such pass-AND gates are provided for each cell, one may be used for the clock signal, and the other for the shift signal. In this manner, only those cells of the shift register, circular pointer or ring counter whose outputs are asserted, or will become asserted during the next shift operation, will present a larger capacitance to the clock and shift signals. All of the other cells will present a smaller capacitance to the clock and shift signals.
摘要翻译： 移位寄存器，圆形指针或环形计数器在时钟上呈现降低的电容性负载，并且用于控制它的移位信号。 使用一个或多个增强数据单元构造该设备。 每个数据单元具有数据输入，数据输出，时钟输入和移位输入。 每个单元的数据输出耦合到相邻单元的数据输入。 为每个单元提供至少一个通过与门。 通门AND门具有开关输入和开关输入。 开关输入用于切换开关输入的输入电容在较大和较小值之间。 每个单元的数据输入和数据输出的逻辑“或”用于驱动该单元的关联的通过与门的切换输入。 通过与门的开关输入适于耦合到时钟（或移位）信号，并且通过与门的输出耦合到数据单元的时钟（或移位）输入。 当为每个单元提供两个这样的通过AND门时，可以使用时钟信号，另一个用于移位信号。 以这种方式，只有移位寄存器的这些单元，其输出被置位的环形指针或环形计数器，或者将在下一个移位操作期间被置为有效，才会给时钟和移位信号带来更大的电容。 所有其他单元将对时钟和移位信号呈现较小的电容。
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公开(公告)号：US06778111B1
公开(公告)日：2004-08-17
申请号：US10653341
申请日：2003-09-02
申请人： Zhubiao Zhu , Kenneth Koch, II
发明人： Zhubiao Zhu , Kenneth Koch, II
IPC分类号： H03M100
CPC分类号： H03K5/088 , H03K3/02337 , H03K5/1252 , H04L25/08
摘要： A system and method provide deglitch filtering. The system has a voltage-based deglitching filter and timing-based deglitching filter. The voltage-based deglitching filter connects with the timing-based deglitch filter, such that the output of the voltage-based deglitch filter connects to the input of the timing-based deglitch filter. The voltage-based deglitch filter is in feedback with the timing based deglitching filter.
摘要翻译： 系统和方法提供deglitch滤波。 该系统具有基于电压的去角度滤波器和基于定时的去角度滤波器。 基于电压的去角滤波器与基于定时的去隙滤波器连接，使得基于电压的去隔离滤波器的输出连接到基于时序的去离子滤波器的输入。 基于电压的deglitch滤波器与基于定时的去角度滤波器反馈。
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公开(公告)号：US07202702B2
公开(公告)日：2007-04-10
申请号：US10732687
申请日：2003-12-10
IPC分类号： H03K19/0175
CPC分类号： H03K19/00384
摘要： A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.
摘要翻译： 由输出缓冲器的电路产生的信号相对于时钟信号被识别，以控制用于输出缓冲器的电路的转换速率。
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公开(公告)号：US07433426B2
公开(公告)日：2008-10-07
申请号：US10831095
申请日：2004-04-23
CPC分类号： H04L25/063 , H03K5/082 , H03K5/1252
摘要： An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.
摘要翻译： 自适应迟滞接收器处理高速数字信号。 差分接收器电路将高速数字信号与参考电压进行比较以产生输出信号。 寄存器电路根据时钟信号锁存输出信号以产生控制信号。 参考电压发生器响应于输出信号和控制信号从限定深滞后电平和浅滞后电平的多个电压产生参考电压。
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5.发明授权Method and system for performing sampling on the fly using minimum cycle delay synchronization 有权使用最小循环延迟同步在飞行中执行采样的方法和系统公开(公告)号：US06734709B1
公开(公告)日：2004-05-11
申请号：US10383127
申请日：2003-03-06
IPC分类号： H03K3017
摘要： A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.
摘要翻译： 一种用于使用最小时钟周期延迟同步在一个或多个集成电路节点上采集集成电路的一个或多个总线域时钟的方法和系统。 当一个或多个总线域时钟需要异步操作时，在飞行电路，设置复位电路和亚稳态抑制电路上的采样用于提供足够的脉冲宽度用于在一个或多个节点上飞行时进行采样。 飞行电路上的采样也可用于在一个或多个节点上同时采样。
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6.发明授权公开(公告)号：US06882201B1
公开(公告)日：2005-04-19
申请号：US10754075
申请日：2004-01-07
CPC分类号： H03K3/0375
摘要： In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.
摘要翻译： 在优选实施例中，本发明提供了一种用于更小和更快的三重冗余锁存器的电路和方法。 输入驱动器连接到两个传输门的输入端。 一个传输门的输出连接到第一锁存器的I / O，第二传输门的输出端连接到第二锁存器的I / O。 第一锁存器的I / O连接到可跟踪输入反相器的第一输入端。 第二锁存器的I / O连接到可跟踪输入反相器的第二输入端。 可跟踪输入反相器的输出端连接到第三个锁存器的I / O和输出驱动器的输入端。
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7.发明授权Driver circuit connected to pulse shaping circuitry and method of operating same 失效驱动电路连接到脉冲整形电路和操作方法公开(公告)号：US06753708B2
公开(公告)日：2004-06-22
申请号：US10167493
申请日：2002-06-13
申请人： Kenneth Koch, II , Mozammel Hossain
发明人： Kenneth Koch, II , Mozammel Hossain
IPC分类号： H03B100
CPC分类号： H03K19/0013 , H03K17/08122 , H03K17/163
摘要： An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.
摘要翻译： 集成电路驱动器包括具有在直流电源端子上彼此串联连接的PFET和NFET的源极漏极路径的输出级。 一对逆变器同时响应PFET和NFET的双电平信号驱动栅电极。 每个逆变器包括一对开关和电阻器，用于将反极性电压源连接到与PFET和NFET的栅电极并联连接的单独电容器。 逆变器，电阻和电容器可以防止PFET和NFET同时导通。
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8.发明授权System and method for controlling delay times in floating-body CMOSFET inverters 失效用于控制浮体CMOSFET逆变器的延迟时间的系统和方法公开(公告)号：US06404243B1
公开(公告)日：2002-06-11
申请号：US09759718
申请日：2001-01-12
申请人： Kenneth Koch, II , William Weiner
发明人： Kenneth Koch, II , William Weiner
IPC分类号： H03B2100
CPC分类号： H03K5/159 , H03K5/133 , H03K19/0013 , H03K19/01707 , H03K2005/00136
摘要： The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.
摘要翻译： 本发明公开了一种用于控制逆变器的延迟时间的体积偏置逆变器的浮体结构CMOSFET逆变器。 在主逆变器的输入端和变频器的FET的主体端子之间连接有至少一个主体偏置逆变器。 通过向p沟道和n沟道FET的体式端子提供输入电压的表示，本发明的优选实施例能够控制与可变源极对体电压相关联的与历史相关的延迟时间 浮体CMOSFET逆变器。 通过向主逆变器电路中添加奇数个体偏置反相器级来延迟时间被最小化。 通过在电路中添加偶数个体偏置反相器级，延迟时间也可以最大化。
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公开(公告)号：US07239185B2
公开(公告)日：2007-07-03
申请号：US10777174
申请日：2004-02-13
申请人： Kenneth Koch, II , Mozammel Hossain
发明人： Kenneth Koch, II , Mozammel Hossain
CPC分类号： H03K19/0013 , H03K17/08122 , H03K17/163
摘要： An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.
摘要翻译： 集成电路驱动器包括具有在直流电源端子上彼此串联连接的PFET和NFET的源极漏极路径的输出级。 一对逆变器同时响应PFET和NFET的双电平信号驱动栅电极。 每个逆变器包括一对开关和电阻器，用于将反极性电压源连接到与PFET和NFET的栅电极并联连接的单独电容器。 逆变器，电阻和电容器可以防止PFET和NFET同时导通。
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公开(公告)号：US07055114B2
公开(公告)日：2006-05-30
申请号：US10681815
申请日：2003-10-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.
摘要翻译： 过程，软件和系统不对称地缩小了VLSI电路设计的布局。 由具有第一设计规则的第一制造过程定义的第一VLSI电路设计布局被不对称地缩放到由具有第二设计规则的第二制造工艺定义的第二VLSI电路设计布局。 处理第二VLSI电路设计布局的一个或多个叶单元的布局以确保符合第二设计规则。
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