公开(公告)号：US07420861B2

公开(公告)日：2008-09-02

申请号：US11558398

申请日：2006-11-09

申请人： Hi-Choon Lee ,  Wol-Jin Lee

发明人： Hi-Choon Lee ,  Wol-Jin Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

摘要翻译： 半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。 还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。 开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。 存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路 达到第二电压电平。

公开(公告)号：US20050146957A1

公开(公告)日：2005-07-07

申请号：US11009248

申请日：2004-12-10

申请人： Hi-Choon Lee ,  Wol-Jin Lee

发明人： Hi-Choon Lee ,  Wol-Jin Lee

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/419

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

摘要翻译： 半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。 还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。 开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。 存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路 达到第二电压电平。

公开(公告)号：US07808852B2

公开(公告)日：2010-10-05

申请号：US12230570

申请日：2008-09-02

申请人： Hyang-Ja Yang ,  Wol-Jin Lee

发明人： Hyang-Ja Yang ,  Wol-Jin Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/18

摘要： Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.

摘要翻译： 示例性实施例涉及半导体存储器件，例如包括有效布局电路的半导体存储器件及其方法。 该方法可以包括在第一预充电器和第二预充电器之间共享第一有效区域并且在第三预充电器和第四预充电器之间共享第二有效区域。 半导体存储器件可以包括电平移位器，其被配置为接收第一预充电控制信号并将第一预充电控制信号的逻辑高电平升高到外部电源电压电平以输出升压的第一预充电控制信号。 半导体存储器件还可以包括第一，第二，第三和第四预充电器。 第一和第三预充电器可以被配置为在数据读取操作期间响应于升压的第一预充电控制信号而将传输到第一和第二对本地输入/输出数据线的数据信号预充电到第一预充电电压。

公开(公告)号：US20090059687A1

公开(公告)日：2009-03-05

申请号：US12230570

申请日：2008-09-02

申请人： Hyang-Ja Yang ,  Wol-Jin Lee

发明人： Hyang-Ja Yang ,  Wol-Jin Lee

IPC分类号： G11C7/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C7/18

摘要： Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.

摘要翻译： 示例性实施例涉及半导体存储器件，例如包括有效布局电路的半导体存储器件及其方法。 该方法可以包括在第一预充电器和第二预充电器之间共享第一有效区域并且在第三预充电器和第四预充电器之间共享第二有效区域。 半导体存储器件可以包括电平移位器，其被配置为接收第一预充电控制信号并将第一预充电控制信号的逻辑高电平升高到外部电源电压电平以输出升压的第一预充电控制信号。 半导体存储器件还可以包括第一，第二，第三和第四预充电器。 第一和第三预充电器可以被配置为在数据读取操作期间响应于升压的第一预充电控制信号而将传输到第一和第二对本地输入/输出数据线的数据信号预充电到第一预充电电压。

公开(公告)号：US07417917B2

公开(公告)日：2008-08-26

申请号：US11590703

申请日：2006-10-31

申请人： Wol-jin Lee ,  Jae-woong Lee

发明人： Wol-jin Lee ,  Jae-woong Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A column decoder of a semiconductor memory device includes an internal address output circuit, an address decoder, and a control circuit. The internal address output circuit converts an external column address into an internal column address and outputs the internal column address. The address decoder decodes a pre-decoded column address, which is obtained by decoding the internal column address, in response to a write column enable signal or in response to a read column enable signal activated earlier than the write column enable signal, and generates a column selection line signal for activating a memory cell designated by the external column address. The control circuit outputs a write signal or a read signal for controlling an output time of the internal column address. The address decoder generates a valid column selection line signal in response to a write signal in the write operation, and generates a valid column selection line signal in response to the read signal in a read operation.

摘要翻译： 半导体存储器件的列解码器包括内部地址输出电路，地址解码器和控制电路。 内部地址输出电路将外部列地址转换为内部列地址，并输出内部列地址。 地址解码器响应于写入列使能信号或响应于早于写入列使能信号激活的读取列使能信号来解码内部列地址解码所获得的预解码列地址，并且生成 用于激活由外部列地址指定的存储单元的列选择线信号。 控制电路输出用于控制内部列地址的输出时间的写信号或读信号。 地址解码器响应于写入操作中的写入信号而生成有效的列选择线信号，并且响应读取操作中的读取信号而生成有效的列选择线信号。

公开(公告)号：US20070115750A1

公开(公告)日：2007-05-24

申请号：US11590703

申请日：2006-10-31

申请人： Wol-jin Lee ,  Jae-woong Lee

发明人： Wol-jin Lee ,  Jae-woong Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A column decoder of a semiconductor memory device includes an internal address output circuit, an address decoder, and a control circuit. The internal address output circuit converts an external column address into an internal column address and outputs the internal column address. The address decoder decodes a pre-decoded column address, which is obtained by decoding the internal column address, in response to a write column enable signal or in response to a read column enable signal activated earlier than the write column enable signal, and generates a column selection line signal for activating a memory cell designated by the external column address. The control circuit outputs a write signal or a read signal for controlling an output time of the internal column address. The address decoder generates a valid column selection line signal in response to a write signal in the write operation, and generates a valid column selection line signal in response to the read signal in a read operation.

摘要翻译： 半导体存储器件的列解码器包括内部地址输出电路，地址解码器和控制电路。 内部地址输出电路将外部列地址转换为内部列地址，并输出内部列地址。 地址解码器响应于写入列使能信号或响应于早于写入列使能信号激活的读取列使能信号来解码内部列地址解码所获得的预解码列地址，并且生成 用于激活由外部列地址指定的存储单元的列选择线信号。 控制电路输出用于控制内部列地址的输出时间的写信号或读信号。 地址解码器响应于写入操作中的写入信号而生成有效的列选择线信号，并且响应读取操作中的读取信号而生成有效的列选择线信号。

公开(公告)号：US20070070749A1

公开(公告)日：2007-03-29

申请号：US11558398

申请日：2006-11-09

申请人： Hi-Choon LEE ,  Wol-Jin LEE

发明人： Hi-Choon LEE ,  Wol-Jin LEE

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

摘要翻译： 半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。 还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。 开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。 存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路 达到第二电压电平。

公开(公告)号：US07154796B2

公开(公告)日：2006-12-26

申请号：US11009248

申请日：2004-12-10

申请人： Hi-Choon Lee ,  Wol-Jin Lee

发明人： Hi-Choon Lee ,  Wol-Jin Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/229

摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

摘要翻译： 半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。 还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。 开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。 存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路 达到第二电压电平。