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公开(公告)号：US12096703B2
公开(公告)日：2024-09-17
申请号：US18009530
申请日：2021-06-29
发明人： Taiwei Chiu , Tingying Shen , Qi Xiang
CPC分类号： H10N70/021 , H10B63/80 , H10N70/063 , H10N70/841
摘要： A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer located in the semiconductor substrate and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the resistive layer has a variable resistance; a first oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the first oxygen grasping layer is located above the resistive layer; a second oxygen grasping layer located in the bottom electrode metal layer, where upper surfaces of the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer are flush, and the resistive layer covers the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer.
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公开(公告)号：US20230225229A1
公开(公告)日：2023-07-13
申请号：US18009525
申请日：2021-06-29
发明人： Taiwei CHIU , Tingying SHEN , He QIAN
CPC分类号： H10N70/8833 , H10N70/841 , H10N70/021 , H10N70/063 , H10B63/80
摘要： A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the resistive layer is greater than the transverse width of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive layer has a variable resistance; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, where the oxygen barrier layer is located above the resistive layer; and an oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the oxygen grasping layer is less than the transverse width of the resistive layer.
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公开(公告)号：US20230110795A1
公开(公告)日：2023-04-13
申请号：US17796166
申请日：2020-11-27
发明人： Ting Ying SHEN , Qi XIANG
IPC分类号： H01L23/528 , H10B63/00
摘要： An integrated circuit and an electronic device, and provides an integrated circuit having better area efficiency. The integrated circuit may be a resistive random access memory, which includes a plurality of resistive memory cells arranged in row and column directions; each resistive memory cell includes a resistive switching unit and a switch unit coupled to the resistive switching unit; the resistive switching units in the column direction are respectively coupled to corresponding source lines; the source lines include first source lines and second source lines; and the first source lines and the second source lines are located on different interconnect layers.
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公开(公告)号：US20240349629A1
公开(公告)日：2024-10-17
申请号：US18292340
申请日：2022-08-18
发明人： Yajun ZHANG , Tingying SHEN , Lijun SHAN , Taiwei CHIU , Yu LIU , Szu-chun KANG
CPC分类号： H10N70/063 , H10B63/30 , H10N70/021 , H10N70/841 , H10N70/8833
摘要： A semiconductor integrated circuit device includes a resistive layer having a trench-like structure with an upward opening, a first electrode located on an outer side of the resistive layer, and a second electrode located on an inner side of the resistive layer; the first electrode and the second electrode are opposite to each other on two sides of a sidewall of the resistive layer; and the resistive layer, the first electrode and the second electrode form a first memory cell. A manufacturing method includes forming a first electrode on a substrate, the substrate including a first via connected with a first metal layer; etching a recess in the first electrode at a position staggered from the first via and forming a resistive layer in the recess; and forming a second electrode in the opening of the resistive layer to obtain a first memory cell.
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公开(公告)号：US12102021B2
公开(公告)日：2024-09-24
申请号：US18009525
申请日：2021-06-29
发明人： Taiwei Chiu , Tingying Shen , He Qian
CPC分类号： H10N70/8833 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/841
摘要： A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the resistive layer is greater than the transverse width of the bottom electrode metal layer and/or the top electrode metal layer, and the resistive layer has a variable resistance; an oxygen barrier layer located between the bottom electrode metal layer and the top electrode metal layer, where the oxygen barrier layer is located above the resistive layer; and an oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the transverse width of the oxygen grasping layer is less than the transverse width of the resistive layer.
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公开(公告)号：US20230225226A1
公开(公告)日：2023-07-13
申请号：US18009530
申请日：2021-06-29
发明人： Taiwei CHIU , Tingying SHEN , Qi XIANG
CPC分类号： H10N70/021 , H10N70/841 , H10N70/063 , H10B63/80
摘要： A semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor substrate; a bottom electrode metal layer located in the semiconductor substrate and a top electrode metal layer located on the semiconductor substrate; a resistive layer located between the bottom electrode metal layer and the top electrode metal layer, where the resistive layer has a variable resistance; a first oxygen grasping layer located between the bottom electrode metal layer and the top electrode metal layer, where the first oxygen grasping layer is located above the resistive layer; a second oxygen grasping layer located in the bottom electrode metal layer, where upper surfaces of the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer are flush, and the resistive layer covers the semiconductor substrate, the bottom electrode metal layer, and the second oxygen grasping layer.
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公开(公告)号：US20230320238A1
公开(公告)日：2023-10-05
申请号：US18329540
申请日：2023-06-05
发明人： Taiwei CHIU , Lijun SHAN , Tingying SHEN
CPC分类号： H10N70/20 , H10B63/20 , H10N70/011 , H10N70/841 , H10N70/826
摘要： The present disclosure provides a semiconductor integrated circuit device and a manufacturing method therefor. In the device, an electrode in a resistive random-access memory (RRAM) cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via with other metal materials (such as tungsten) and of polishing. The manufacturing process is hence simplified, and different degrees of depressions caused by polishing are correspondingly reduced. The uniformity of resistive performance of the RRAM and the quality of the semiconductor integrated circuit device are hence greatly improved. In addition, a resistive layer having a trench structure is formed by using a trench where an original connection via is located, thereby embedding the entire RRAM cell into the trench. The structure of the RRAM cell is more compact, a gap between RRAM cells is smaller, and the requirements for miniaturization and high density can thus be better met.
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公开(公告)号：US20240251686A1
公开(公告)日：2024-07-25
申请号：US18426367
申请日：2024-01-30
发明人： SZU-CHUN KANG , Tingying SHEN , Lijun SHAN , Taiwei CHIU , Yu LIU , Yajun ZHANG
CPC分类号： H10N70/823 , H10N70/011 , H10N70/24
摘要： Disclosed in embodiments of the present application are a linear resistive element and a preparation method therefor. The linear resistive element includes a substrate unit, a function unit and an electrode unit. The substrate unit includes a substrate layer, which is configured to connect the function unit and the electrode unit. The electrode unit includes a first electrode and a second electrode. The first and second electrodes are deposited on the substrate layer, and the function unit is connected between the first and second electrodes. The function unit includes first dielectric layers and resistive layers. The first dielectric layers and the resistive layers are deposited on the substrate layer in an alternately stacked manner. A number of the resistive layers is at least two, and a conductive filament for conductively connecting the first and second electrodes is formed in each of the resistive layers.
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