公开(公告)号：US20240153559A1

公开(公告)日：2024-05-09

申请号：US18417729

申请日：2024-01-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Der CHIH ,  Chung-Cheng CHOU ,  Wen-Ting CHU

IPC分类号： G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  H10B63/30 ,  H10B63/80 ,  H10B63/84 ,  H10N70/253 ,  H10N70/841 ,  G11C13/0007 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H10N70/20 ,  H10N70/826 ,  H10N70/8833

摘要： A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

公开(公告)号：US20230422640A1

公开(公告)日：2023-12-28

申请号：US18463777

申请日：2023-09-08

申请人： KIOXIA CORPORATION

发明人： Kenichi MUROOKA

IPC分类号： H10N70/00 ,  G11C8/10 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/826 ,  G11C8/10 ,  G11C13/0002 ,  H10B63/80 ,  H10B63/845 ,  H10N70/20 ,  H10N70/021 ,  H10N70/823 ,  H10N70/8833 ,  H10N70/8836 ,  H10N70/8845 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2

公开(公告)号：US20230380306A1

公开(公告)日：2023-11-23

申请号：US18362781

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fu-Ting SUNG ,  Chern-Yow HSU ,  Shih-Chang LIU

IPC分类号： H10N70/20 ,  H10N50/01 ,  H10N70/00

CPC分类号： H10N70/24 ,  H10N50/01 ,  H10N70/011 ,  H10N70/20 ,  H10N70/063 ,  H10N70/801 ,  H10N70/826

摘要： A memory device includes a first metal structure, a magnetic tunnel junction (MTJ) structure, a second metal structure, a first spacer, and a second spacer. The MTJ structure is over the first metal structure. The second metal structure is over the MTJ structure. The first spacer is over a first sidewall of the second metal structure. The second spacer is over a second sidewall of the second metal structure. The second spacer has a top surface higher than a top surface of the first spacer.

公开(公告)号：US20230371396A1

公开(公告)日：2023-11-16

申请号：US18357332

申请日：2023-07-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC分类号： H10N50/80 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N50/80 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/011 ,  H10N70/20 ,  H10N70/021 ,  H10N70/063 ,  H10N70/826 ,  H10N70/8833

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

公开(公告)号：US11800825B2

公开(公告)日：2023-10-24

申请号：US17584868

申请日：2022-01-26

申请人： Kioxia Corporation

发明人： Kenichi Murooka

IPC分类号： G11C8/10 ,  G11C13/00 ,  H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/826 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  H10B63/80 ,  H10B63/845 ,  H10N70/021 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833 ,  H10N70/8836 ,  H10N70/8845 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2

公开(公告)号：US11800822B2

公开(公告)日：2023-10-24

申请号：US17572599

申请日：2022-01-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC分类号： H10N70/20 ,  H10N50/01 ,  H10N70/00

CPC分类号： H10N70/24 ,  H10N50/01 ,  H10N70/011 ,  H10N70/063 ,  H10N70/20 ,  H10N70/801 ,  H10N70/826

摘要： A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.

公开(公告)号：US20230320238A1

公开(公告)日：2023-10-05

申请号：US18329540

申请日：2023-06-05

申请人： XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.

发明人： Taiwei CHIU ,  Lijun SHAN ,  Tingying SHEN

IPC分类号： H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/20 ,  H10B63/20 ,  H10N70/011 ,  H10N70/841 ,  H10N70/826

摘要： The present disclosure provides a semiconductor integrated circuit device and a manufacturing method therefor. In the device, an electrode in a resistive random-access memory (RRAM) cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via with other metal materials (such as tungsten) and of polishing. The manufacturing process is hence simplified, and different degrees of depressions caused by polishing are correspondingly reduced. The uniformity of resistive performance of the RRAM and the quality of the semiconductor integrated circuit device are hence greatly improved. In addition, a resistive layer having a trench structure is formed by using a trench where an original connection via is located, thereby embedding the entire RRAM cell into the trench. The structure of the RRAM cell is more compact, a gap between RRAM cells is smaller, and the requirements for miniaturization and high density can thus be better met.

公开(公告)号：US20240188457A1

公开(公告)日：2024-06-06

申请号：US18527152

申请日：2023-12-01

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Sergiu CLIMA ,  Taras RAVSHER ,  Geoffrey POURTOIS

IPC分类号： H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8828 ,  H10B63/24 ,  H10N70/023 ,  H10N70/026 ,  H10N70/20

摘要： In one aspect, a device includes a threshold switch formed of a mixture. The mixture includes at least 0.90 parts by mole of a composition of three or four chemical elements of: from 0.20 to 0.70 parts by mole of Si, from 0.05 to 0.60 parts by mole of Te, and from 0.05 to 0.60 parts by mole of S, P, or a mixture of S and P. The mixture also includes at most 0.10 parts by mole of optional other chemical elements different from Si, Te, S, and P. The parts by mole of the mixture add up to 1.00.

公开(公告)号：US11956976B2

公开(公告)日：2024-04-09

申请号：US18234368

申请日：2023-08-15

申请人： Monolithic 3D Inc.

发明人： Deepak C. Sekar ,  Zvi Or-Bach

IPC分类号： H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/00 ,  H01L27/105 ,  H10B41/40 ,  H10B43/40 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

摘要： A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.

公开(公告)号：US11848052B2

公开(公告)日：2023-12-19

申请号：US17704041

申请日：2022-03-25

申请人： ZHEJIANG UNIVERSITY

发明人： Yi Zhao ,  Bing Chen

IPC分类号： G11C13/00 ,  G11C15/04 ,  H10N70/20

CPC分类号： G11C15/046 ,  H10N70/20

摘要： The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line. The present disclosure can greatly reduce a chip dimension of the ternary content addressable memory and reduce power consumption; the ternary content addressable memory of the present disclosure has a simple structure, which effectively simplifies a manufacturing process and reduces a manufacturing cost; the present disclosure provides and achieves a memory diode that is compatible with a standard CMOS process, which is suitable for currently rapidly developing semiconductor integrated circuits.