公开(公告)号：US09729447B2

公开(公告)日：2017-08-08

申请号：US15140424

申请日：2016-04-27

申请人： Xpliant, Inc.

发明人： Weihuang Wang ,  Mohan Balan ,  Nimalan Siva ,  Zubin Shah

IPC分类号： H04L12/28 ,  H04L12/745 ,  H04L12/753 ,  H04L12/749

CPC分类号： H04L45/748 ,  H04L45/48 ,  H04L45/741

摘要： A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.

公开(公告)号：US20160292091A1

公开(公告)日：2016-10-06

申请号：US14673828

申请日：2015-03-30

申请人： XPLIANT, Inc.

发明人： Enrique Musoll ,  Tsahi Daniel

IPC分类号： G06F13/16 ,  G06F13/40

CPC分类号： G06F13/1663 ,  G06F13/161 ,  G06F13/1673 ,  G06F13/4022 ,  H04L45/126 ,  H04L49/9005

摘要： A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

摘要翻译： 具有多个分级客户机中的每一个的分组处理系统和经由多个主接口串行通信地耦合在一起的分组存储器仲裁器，从而形成单向客户端链。 然后，该链可以被所有层级客户端利用来将分组数据写入或从分组存储器读取分组数据。

公开(公告)号：US09443053B2

公开(公告)日：2016-09-13

申请号：US14141096

申请日：2013-12-26

申请人： XPLIANT, Inc.

发明人： Nikhil Jayakumar ,  Vivek Trivedi ,  Vasant K. Palisetti ,  Bhagavati R. Mula ,  Daman Ahluwalia ,  Amir H. Motamedi

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5009 ,  G06F17/5072 ,  G06F2217/62 ,  G06F2217/84

摘要： Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.

摘要翻译： 混合树网时钟分配网络中的时钟站使用嵌入在构成时钟分配网络的宏小区的实例名称中的放置信息进行放置和路由。 实例名称包括对应于宏小区在网络设计的物理布局中的放置的（X，Y）坐标信息。 每个宏单元中的基本单元以已知的确定性排列方式放置，例如在时钟分配网络的布局中的另一个，全部处于相同的（X，Y）偏移。 优选地，基本单元都来自标准单元库，从而降低了设计成本和调试。

公开(公告)号：US20160139898A1

公开(公告)日：2016-05-19

申请号：US14675696

申请日：2015-03-31

申请人： XPLIANT, Inc

发明人： Ajeer Salil Pudiyapura ,  Kishore Badari Atreya ,  Ravindran Suresh

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F8/33 ,  G06F8/314 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4434 ,  G06F8/445 ,  G06F8/447 ,  G06F8/451 ,  G06F8/70 ,  G06F9/30145 ,  G06F15/76 ,  G06F15/7825

摘要： A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

摘要翻译： 一种包括多个查找和决策引擎（LDE）的处理网络，每个查找和决策引擎（LDE）具有一个或多个配置寄存器和多个片上路由器，所述多个片上路由器形成用于在LDE之间路由数据的矩阵，其中每个片上路由器是可通信的 加上一个或多个LDE。 处理网络还包括存储在存储器中并与每个LDE通信耦合的LDE编译器，其中，LDE编译器被配置为基于输入源代码生成值，当编程到LDE的配置寄存器中时，使LDE实现 由输入源代码定义的功能。

公开(公告)号：US20160087809A1

公开(公告)日：2016-03-24

申请号：US14494168

申请日：2014-09-23

申请人： XPLIANT, Inc

发明人： Gerald Schmidt ,  Harish Krishnamoorthy ,  Tsahi Daniel

IPC分类号： H04L12/18 ,  H04L12/883 ,  H04L12/933 ,  H04L12/715 ,  G06F17/30 ,  H04L29/08

CPC分类号： H04L45/04 ,  G06F17/30575 ,  G06F17/30958 ,  G06F2205/064 ,  H04L12/1854 ,  H04L12/1886 ,  H04L49/109 ,  H04L49/201 ,  H04L49/9015 ,  H04L67/1095

摘要： A multicast rule is represented in a hierarchical linked list with N tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. Redundant groups in each tier are eliminated such that the groups in each tier are stored exactly once in a replication table. A multicast replication engine traverses the hierarchical linked list and replicates a packet according to each node in the hierarchical linked list.

摘要翻译： 组播规则在具有N个层的分层链表中表示。 分层链表中的每个层或层级对应于需要复制的网络堆栈的网络层。 消除每个层中的冗余组，使每个层中的组在复制表中保存一次。 组播复制引擎遍历分层链表，并根据分层链表中的每个节点复制数据包。

公开(公告)号：US09262369B1

公开(公告)日：2016-02-16

申请号：US14676791

申请日：2015-04-01

申请人： Xpliant, Inc.

发明人： Tsahi Daniel ,  Enric Musoll ,  Dan Tu ,  Sridevi Polasanapalli

IPC分类号： G06F13/28 ,  G06F15/167 ,  H04L12/825

CPC分类号： G06F15/167 ,  G06F3/0611 ,  H04L47/25 ,  H04L49/90 ,  H04L49/9094

摘要： A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

公开(公告)号：US20150373166A1

公开(公告)日：2015-12-24

申请号：US14309802

申请日：2014-06-19

申请人： XPLIANT, Inc.

发明人： Vishal Anand ,  Tsahi Daniel ,  Gerald Schmidt ,  Premshanth Theivendran

IPC分类号： H04L29/06 ,  H04L12/741

CPC分类号： H04L45/745 ,  H04L45/7453 ,  H04L45/7457 ,  H04L69/161 ,  H04L69/22

摘要： Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

摘要翻译： 识别网络分组的内部目的地的装置的实施例涉及允许处理分组的灵活性的网络芯片。 分组的处理可以是分组内容是什么或分组来自哪里的功能。 分组的处理也可以是分组内容和分组来自哪里的功能。 在一些实施例中，分组来自的是指分组到达的芯片端口的唯一端口号。 分组可以分布在网络芯片内进行处理。

公开(公告)号：US20150186583A1

公开(公告)日：2015-07-02

申请号：US14141104

申请日：2013-12-26

申请人： XPLIANT, Inc.

发明人： Nikhil Jayakumar ,  Vivek Trivedi ,  Vasant K. Palisetti ,  Bhagavati R. Mula ,  Daman Ahluwalia ,  Amir H. Motamedi

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84

摘要： Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.

摘要翻译： 采用可变驱动强度时钟驱动器构建的时钟网络可用于调谐。 时钟驱动器是由较小的基准标准单元组成的。 即使通过提取过程，宏单元的输入和输出网表的位置也被标记和保留。 宏单元能够被平坦化，产生具有基本单元的网表，并且在电路仿真期间重组，从而减少迭代次数，使得调谐流程更有效率。 时钟网络最初通过添加或删除网格中的交叉链路进行调谐，以平衡时钟网格的每个驱动程序上的容性负载。

公开(公告)号：US20150186516A1

公开(公告)日：2015-07-02

申请号：US14144270

申请日：2013-12-30

申请人： XPLIANT, INC.

发明人： Anh T. Tran ,  Gerald Schmidt ,  Tsahi Daniel ,  Harish Krishnamoorthy

IPC分类号： G06F17/30

CPC分类号： H04L45/745 ,  G06F17/30 ,  G06F17/30321 ,  G06F17/30339 ,  G06F17/30867 ,  H04L45/00 ,  H04L45/74

摘要： Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.

摘要翻译： 本发明的实施例涉及一种用于生成用于输入令牌的查找密钥并基于查找结果的内容修改输入令牌的查找和决策引擎（LDE）。 输入令牌由解析器从网络数据包头解析，令牌由LDE修改。 修改的令牌指导如何在软件定义网络（SDN）系统中由其他组件修改或转发相应的网络数据包。 LDE的设计非常灵活，与协议无关。 用于生成查找键和修改令牌的条件和规则是完全可编程的，使得LDE可以在SDN系统中执行各种可重新配置的网络特征和协议。

公开(公告)号：US20160294729A1

公开(公告)日：2016-10-06

申请号：US14673807

申请日：2015-03-30

申请人： XPLIANT, Inc.

发明人： Enrique Musoll

IPC分类号： H04L12/933 ,  H04L12/18 ,  H04L12/935

CPC分类号： H04L49/103 ,  G06F12/0607 ,  G06F2212/1024 ,  G06F2212/1044 ,  H04L12/1881 ,  H04L49/30

摘要： A packet memory system for selectively outputting received packets on one or more output ports. The packet memory system including a controller for controlling the output ports. Specifically, for packets of multicast or broadcast traffic that needs to be output from a plurality of the ports, the controller designates one or more reader ports that read the packet data from a packet memory such that the remainder of the ports are able to simply listen for the read packet data without performing a read operation.

摘要翻译： 一种分组存储器系统，用于在一个或多个输出端口上选择性地输出接收的分组。 分组存储器系统包括用于控制输出端口的控制器。 具体来说，对于需要从多个端口输出的组播或广播流量的分组，控制器指定从分组存储器读取分组数据的一个或多个读取器端口，使得其余端口能够简单地听 对于读取的分组数据而不执行读取操作。