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公开(公告)号：US20080197830A1
公开(公告)日：2008-08-21
申请号：US11951565
申请日：2007-12-06
Applicant: GUSTAVO JAMES MEHAS , SANDEEP AGARWAL , JAYANT VIVREKAR , XIAOLE CHEN
Inventor： GUSTAVO JAMES MEHAS , SANDEEP AGARWAL , JAYANT VIVREKAR , XIAOLE CHEN
CPC classification number: H03L7/0992 , H03L7/085 , H03L7/093
Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Abstract translation: 电路包括用于产生同步信号的数字锁相环和用于响应于来自数字锁相环的同步信号来提供调节的输出电压的电压调节器。
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公开(公告)号：US20100007391A1
公开(公告)日：2010-01-14
申请号：US12564466
申请日：2009-09-22
Applicant: GUSTAVO JAMES MEHAS , SANDEEP AGARWAL , JAYANT VIVREKAR , XIAOLE CHEN
Inventor： GUSTAVO JAMES MEHAS , SANDEEP AGARWAL , JAYANT VIVREKAR , XIAOLE CHEN
IPC: H03L7/08
CPC classification number: H03L7/0992 , H03L7/085 , H03L7/093
Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Abstract translation: 电路包括用于产生同步信号的数字锁相环和用于响应于来自数字锁相环的同步信号来提供调节的输出电压的电压调节器。
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公开(公告)号：US07205798B1
公开(公告)日：2007-04-17
申请号：US11045929
申请日：2005-01-28
Applicant: Sandeep Agarwal , Xiaole Chen
Inventor： Sandeep Agarwal , Xiaole Chen
IPC: H03B21/00
CPC classification number: H03L7/0994 , G06F1/025 , H03L7/081 , H03L7/18
Abstract: Circuits, methods, and apparatus for reducing the phase error in an NCO clock output to reduce the clock jitter. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to obtain a substantially glitch-free, high-speed operation. During the first step, the output of the NCO is phase shifted to the closest quarter portion of a cycle of a clock signal. A second correction step is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.
Abstract translation: 用于减少NCO时钟输出中的相位误差的电路，方法和装置，以减少时钟抖动。 这在NCO输出和参考信号的频率无关的情况下尤其有利。 一个实施例提供了一种电路，其以两个步骤校正NCO输出的相位，以便获得基本上无毛刺的高速操作。 在第一步骤期间，NCO的输出被相移到时钟信号周期的最近四分之一部分。 然后通过在来自NCO的多个剩余位中的至少一些的控制下转向多个电流来执行第二校正步骤。 目前的转向器提供了芯片区域有效的低噪声相位校正。 使用防止设备进入锁定状态的前馈电路来锁定解码的余数位。
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4.发明授权Highly-linear continuous-time filter for a 3-volt supply with PLL-controlled resistor and digitally-controlled capacitor 失效具有PLL控制电阻和数字控制电容器的3伏电源的高线性连续时间滤波器
公开(公告)号：US6097244A
公开(公告)日：2000-08-01
申请号：US215508
申请日：1998-12-17
Applicant: Xiaole Chen
Inventor： Xiaole Chen
CPC classification number: H03L7/0805 , H03H11/04 , H03H19/004 , H03J7/04 , H03L7/06
Abstract: A continuous-time filter is highly linear even when used with reduced 3-volt power supplies. In each stage of a multi-stage ladder network, resistor networks are attached to each input of a differential op amp. Each resistor network uses fixed resistors in series between the inputs and an intermediate node, and a fixed input resistor between the intermediate node and the op-amp input. The fixed input resistor improves linearity compared with a linear transistor. A transistor connects the internal node to ground, acting as a variable resistor to adjust the equivalent resistance of the resistor network. A control voltage applied to the gate of the transistor is generated by an analog control loop. The control voltage is the voltage input to a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL). The analog PLL control loop adjusts the control voltage and the resistance continuously as the filter operates. A voltage comparator detects when the control voltage is out of a range, activating a calibration signal. Filtering stops and a digital successive-approximation register adjusts capacitances of feedback capacitors around the op amps. The capacitance in the VCO is also adjusted, changing the control voltage. Capacitance converges to the desired value by comparing the control voltage to a mid-range target voltage.
Abstract translation: 连续时间滤波器即使在降低3伏电源的情况下也是高度线性的。 在多级梯形网络的每个阶段，电阻网络连接到差分运算放大器的每个输入。 每个电阻网络使用输入和中间节点之间串联的固定电阻，以及中间节点和运算放大器输入之间的固定输入电阻。 与线性晶体管相比，固定输入电阻提高了线性度。 晶体管将内部节点连接到地，用作可变电阻来调节电阻网络的等效电阻。 施加到晶体管的栅极的控制电压由模拟控制回路产生。 控制电压是在锁相环（PLL）中输入到压控振荡器（VCO）的电压。 模拟PLL控制环路随着滤波器的运行而连续调节控制电压和电阻。 电压比较器检测控制电压何时超出范围，激活校准信号。 滤波停止和数字逐次逼近寄存器调整运算放大器周围的反馈电容的电容。 也调整VCO中的电容，改变控制电压。 通过将控制电压与中等范围的目标电压进行比较，电容收敛到所需的值。
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5.发明授权System and method for programming and controlling over current trip point limits in voltage regulators 有权用于编程和控制电压调节器中过流跳闸点限制的系统和方法公开(公告)号：US08638532B2
公开(公告)日：2014-01-28
申请号：US13532084
申请日：2012-06-25
Applicant: Gustavo James Mehas , Atul Wokhlu , Naveen Jain , Xiaole Chen
Inventor： Gustavo James Mehas , Atul Wokhlu , Naveen Jain , Xiaole Chen
CPC classification number: H02M1/32 , H02M3/155 , H02M2001/0012 , H02M2001/0022
Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
Abstract translation: 用于控制电压调节器的过电流保护跳变点的系统和方法包括用于接收监控的电压调节器的操作参数的输入端。 响应于该输入的控制逻辑产生数字电流控制信号。 数字到模拟控制器将数字电流控制信号转换为模拟电流控制信号，该模拟电流控制信号用于控制电流源以产生建立电压调节器的过流保护跳变点的电流。
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Patent Agency Ranking
公开(公告)号：US08159276B2
公开(公告)日：2012-04-17
申请号：US12564466
申请日：2009-09-22
Applicant: Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
Inventor： Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
IPC: H03L7/06
CPC classification number: H03L7/0992 , H03L7/085 , H03L7/093
Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Abstract translation: 电路包括用于产生同步信号的数字锁相环和用于响应于来自数字锁相环的同步信号来提供调节的输出电压的电压调节器。
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公开(公告)号：US07592846B2
公开(公告)日：2009-09-22
申请号：US11951565
申请日：2007-12-06
Applicant: Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
Inventor： Gustavo James Mehas , Sandeep Agarwal , Jayant Vivrekar , Xiaole Chen
IPC: H03L7/06
CPC classification number: H03L7/0992 , H03L7/085 , H03L7/093
Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.
Abstract translation: 电路包括用于产生同步信号的数字锁相环和用于响应于来自数字锁相环的同步信号来提供调节的输出电压的电压调节器。
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公开(公告)号：US5570049A
公开(公告)日：1996-10-29
申请号：US453413
申请日：1995-05-30
Applicant: Xiaole Chen
Inventor： Xiaole Chen
CPC classification number: H03F1/3211
Abstract: A circuit technique for improving high frequency performance of current-controlled transconductor elements in transconductance-capacitance (g.sub.m -C) based monolithic filters. The circuit detects the output impedance of the transconductance transistors inside the transconductor element, regenerates and applies a negative conductance to the output of the transconductor. By cancelling the transistor output impedance, the total differential mode output impedance of the transconductor element can be maximized.
Abstract translation: 一种用于改善基于跨导电容（gm-C）的单片滤波器中电流控制跨导元件的高频性能的电路技术。 该电路检测跨导元件内的跨导晶体管的输出阻抗，再生并向跨导体的输出施加负电导。 通过消除晶体管输出阻抗，可以使跨导元件的总差模输出阻抗最大化。
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9.发明申请SYSTEM AND METHOD FOR PROGRAMMING AND CONTROLLING OVER CURRENT TRIP POINT LIMITS IN VOLTAGE REGULATORS 有权用于在电压调节器中编程和控制电流限制点的系统和方法公开(公告)号：US20080297957A1
公开(公告)日：2008-12-04
申请号：US12032328
申请日：2008-02-15
Applicant: GUSTAVO JAMES MEHAS , ATUL WOKHLU , NAVEEN JAIN , XIAOLE CHEN
Inventor： GUSTAVO JAMES MEHAS , ATUL WOKHLU , NAVEEN JAIN , XIAOLE CHEN
IPC: H02H9/00
CPC classification number: H02M1/32 , H02M3/155 , H02M2001/0012 , H02M2001/0022
Abstract: A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that establishes the over current protection trip point of the voltage regulator.
Abstract translation: 用于控制电压调节器的过电流保护跳变点的系统和方法包括用于接收监控的电压调节器的操作参数的输入端。 响应于该输入的控制逻辑产生数字电流控制信号。 数字到模拟控制器将数字电流控制信号转换为模拟电流控制信号，该模拟电流控制信号用于控制电流源以产生建立电压调节器的过流保护跳变点的电流。
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10.发明授权
公开(公告)号：US5703524A
公开(公告)日：1997-12-30
申请号：US631900
申请日：1996-04-16
Applicant: Xiaole Chen
Inventor： Xiaole Chen
Abstract: A programmable gain amplifier which can be realized using CMOS transistors. The amplifier provides a plurality of linear gain segments, with each of the gain segments having a different gain. A particular combination of the gain segments are selected using a digital control input to give an approximation of a linear dB output. By appropriately choosing the segments and how they combine, an approximation that is accurate to the least significant bit of a digital system can be provided.
Abstract translation: 可使用CMOS晶体管实现的可编程增益放大器。 放大器提供多个线性增益段，每个增益段具有不同的增益。 使用数字控制输入来选择增益段的特定组合以给出线性dB输出的近似值。 通过适当地选择段和如何组合，可以提供对于数字系统的最低有效位精确的近似。
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