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公开(公告)号：US08835206B2
公开(公告)日：2014-09-16
申请号：US13537025
申请日：2012-06-28
Applicant: Chin-Tzu Kao , Jin-Chuan Kuo , Ya-Ju Lu
Inventor： Chin-Tzu Kao , Jin-Chuan Kuo , Ya-Ju Lu
CPC classification number: H01L27/124 , H01L29/458
Abstract: The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain.
Abstract translation: 本发明提供一种像素结构，其包括基板，第一金属图案层，绝缘层，第二金属图案层，钝化层和导电保护层。 衬底具有至少一个像素区域。 第一图案化金属层设置在基板上，并且具有顶表面。 绝缘层设置在第一图案化金属层和基板上，并且与第一图案化金属层的顶表面接触。 第二图案化金属层设置在像素区域中的绝缘层上，并且包括源极和漏极。 钝化层设置在第二图案化金属层和绝缘层上。 源极的顶表面与钝化层接触，并且导电保护层设置在漏极上。
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公开(公告)号：US07816194B2
公开(公告)日：2010-10-19
申请号：US12544231
申请日：2009-08-20
Applicant: Ya-Ju Lu , Jun-Yao Huang , Ming-Chu Chen , Yu-Fang Wang , Chun-Jen Ma
Inventor： Ya-Ju Lu , Jun-Yao Huang , Ming-Chu Chen , Yu-Fang Wang , Chun-Jen Ma
IPC: H01L21/84
CPC classification number: H01L29/66765 , H01L27/1255 , H01L27/1288
Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.
Abstract translation: 提供一种制造薄膜晶体管的方法，其中制造方法包括岛状半导体的新的蚀刻工艺。 岛状半导体的新的蚀刻工艺由蚀刻气体的流量和蚀刻功率的调节来控制。 当蚀刻岛状半导体时，同时蚀刻露出岛状半导体的栅极绝缘层的一部分。 因此，存储电容电极上的栅极绝缘层的厚度减小，像素电极和辅助电容电极之间的距离减小，并且像素的存储电容增加。 最后，适当降低了存储电容电极的宽度，增加了产品的开口率。
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公开(公告)号：US20100227442A1
公开(公告)日：2010-09-09
申请号：US12544231
申请日：2009-08-20
Applicant: Ya-Ju Lu , Jun-Yao Huang , Ming-Chu Chen , Yu-Fang Wang , Chun-Jen Ma
Inventor： Ya-Ju Lu , Jun-Yao Huang , Ming-Chu Chen , Yu-Fang Wang , Chun-Jen Ma
IPC: H01L21/336
CPC classification number: H01L29/66765 , H01L27/1255 , H01L27/1288
Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.
Abstract translation: 提供一种制造薄膜晶体管的方法，其中制造方法包括岛状半导体的新的蚀刻工艺。 岛状半导体的新的蚀刻工艺由蚀刻气体的流量和蚀刻功率的调节来控制。 当蚀刻岛状半导体时，同时蚀刻露出岛状半导体的栅极绝缘层的一部分。 因此，存储电容电极上的栅极绝缘层的厚度减小，像素电极和辅助电容电极之间的距离减小，并且像素的存储电容增加。 最后，适当降低了存储电容电极的宽度，增加了产品的开口率。
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公开(公告)号：US20130112977A1
公开(公告)日：2013-05-09
申请号：US13537025
申请日：2012-06-28
Applicant: Chin-Tzu Kao , Jin-Chuan Kuo , Ya-Ju Lu
Inventor： Chin-Tzu Kao , Jin-Chuan Kuo , Ya-Ju Lu
CPC classification number: H01L27/124 , H01L29/458
Abstract: The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain.
Abstract translation: 本发明提供一种像素结构，其包括基板，第一金属图案层，绝缘层，第二金属图案层，钝化层和导电保护层。 衬底具有至少一个像素区域。 第一图案化金属层设置在基板上，并且具有顶表面。 绝缘层设置在第一图案化金属层和基板上，并且与第一图案化金属层的顶表面接触。 第二图案化金属层设置在像素区域中的绝缘层上，并且包括源极和漏极。 钝化层设置在第二图案化金属层和绝缘层上。 源极的顶表面与钝化层接触，并且导电保护层设置在漏极上。
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