公开(公告)号：US20130326097A1

公开(公告)日：2013-12-05

申请号：US13984428

申请日：2012-02-17

申请人： Kenichi Shimizu ,  Toshihiro Morita ,  Yasuhiro Ami

发明人： Kenichi Shimizu ,  Toshihiro Morita ,  Yasuhiro Ami

IPC分类号： G06F13/40

CPC分类号： G06F13/4063 ,  G06F13/122 ,  G06F2213/0026

摘要： A semiconductor device capable of implementing system configurations corresponding to various PCIe topologies is provided. A RAM stores one or more configuration registers that define function information of a PCIe device. A Link control unit decodes a request received from a PCIe host and outputs a decoded result to a CPU. The CPU reads a corresponding configuration register from the RAM based on the decoded result received from the Link control unit, and generates a response to the request and causes the Link control unit to transmit the response. Thus, system configurations corresponding to various PCIe topologies can be implemented.

摘要翻译： 提供能够实现与各种PCIe拓扑相对应的系统配置的半导体器件。 RAM存储定义PCIe设备的功能信息的一个或多个配置寄存器。 链路控制单元解码从PCIe主机接收到的请求，并将解码的结果输出到CPU。 CPU基于从链路控制单元接收到的解码结果从RAM读取相应的配置寄存器，并产生对该请求的响应，并使链路控制单元发送响应。 因此，可以实现与各种PCIe拓扑相对应的系统配置。

公开(公告)号：US07957229B2

公开(公告)日：2011-06-07

申请号：US12007465

申请日：2008-01-10

申请人： Yasuhiro Ami

发明人： Yasuhiro Ami

IPC分类号： G11B27/10

CPC分类号： G11B20/10527 ,  G11B19/041 ,  G11B20/10 ,  G11B2020/10675 ,  G11B2020/10685 ,  G11B2020/10694 ,  G11B2020/10833 ,  G11B2020/1222 ,  G11B2020/1267 ,  G11B2220/2541 ,  G11B2220/2575

摘要： An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

摘要翻译： 本发明的目的是提供一种光盘控制器和光盘驱动器系统，其减少了在写入光盘时补充不足的数据的进行时间。 本发明涉及光盘控制器和光盘驱动系统。 光盘控制器包括接口电路，缓冲器，存储器管理器，ECC电路，调制电路和操作处理器。 存储器管理器具有控制寄存器部分，拷贝传送控制器和缓冲器控制器。 控制寄存器部分还包括复制扇区号设置寄存器，用于从操作处理器的控制信号取出并保存多个扇区号不足数据的信息。 复制传送控制器基于扇区号信息连续进行多个扇区号的复制传送处理。

公开(公告)号：US5828898A

公开(公告)日：1998-10-27

申请号：US470650

申请日：1995-06-06

申请人： Yasuhiro Ami ,  Takeshi Fujii

发明人： Yasuhiro Ami ,  Takeshi Fujii

IPC分类号： G06F13/38 ,  G06F9/38 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F9/3879 ,  G06F15/7814 ,  G06F15/7832

摘要： A microcomputer includes an input terminal, coupled to the control terminal of a transmission gate, that receives a real-time request signal asserted by a peripheral. The transmission gate transfers data from a register to the peripheral in synchronism with the assertion of the real-time request signal so that data is provided to the peripheral in real time.

摘要翻译： 微型计算机包括耦合到传输门控的控制终端的输入端，其接收由外设断言的实时请求信号。 传输门与实时请求信号的断言同步地将数据从寄存器传送到外设，以便实时地向外设提供数据。

公开(公告)号：US5579410A

公开(公告)日：1996-11-26

申请号：US262051

申请日：1994-06-17

申请人： Yasuhiro Ami ,  Tadahiko Komatsu

发明人： Yasuhiro Ami ,  Tadahiko Komatsu

IPC分类号： G06T11/40 ,  G09G5/393 ,  G06K9/46

CPC分类号： G09G5/393 ,  G06T11/40

摘要： In the region filling circuit of this invention, if only the starting position and the end position of the filling region rare supplied from outside, the inversion of bits in the filling area including the starting position and the end position where the whole bits are possibly not the subject of filling can be executed by hardware independently of a CPU, thereby to shorten the filling time and consequently reducing the time when the CPU is occupied during the filling.

摘要翻译： 在本发明的区域填充电路中，如果只有从外部稀少提供的填充区域的起始位置和结束位置，包括起始位置和整个位可能不在的结束位置的填充区域中的位的反转 可以通过独立于CPU的硬件执行填充对象，从而缩短填充时间，从而减少在填充期间CPU被占用的时间。

公开(公告)号：US20110205875A1

公开(公告)日：2011-08-25

申请号：US13098903

申请日：2011-05-02

申请人： Yasuhiro Ami

发明人： Yasuhiro Ami

IPC分类号： G11B19/02

CPC分类号： G11B20/10527 ,  G11B19/041 ,  G11B20/10 ,  G11B2020/10675 ,  G11B2020/10685 ,  G11B2020/10694 ,  G11B2020/10833 ,  G11B2020/1222 ,  G11B2020/1267 ,  G11B2220/2541 ,  G11B2220/2575

摘要： An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

摘要翻译： 本发明的目的是提供一种光盘控制器和光盘驱动器系统，其减少了在写入光盘时补充不足的数据的进行时间。 本发明涉及光盘控制器和光盘驱动系统。 光盘控制器包括接口电路，缓冲器，存储器管理器，ECC电路，调制电路和操作处理器。 存储器管理器具有控制寄存器部分，拷贝传送控制器和缓冲器控制器。 控制寄存器部分还包括复制扇区号设置寄存器，用于从操作处理器的控制信号取出并保存多个扇区号不足数据的信息。 复制传送控制器基于扇区号信息连续进行多个扇区号的复制传送处理。

公开(公告)号：US20080175114A1

公开(公告)日：2008-07-24

申请号：US12007465

申请日：2008-01-10

申请人： Yasuhiro AMI

发明人： Yasuhiro AMI

IPC分类号： G11B19/02 ,  G11B20/10

CPC分类号： G11B20/10527 ,  G11B19/041 ,  G11B20/10 ,  G11B2020/10675 ,  G11B2020/10685 ,  G11B2020/10694 ,  G11B2020/10833 ,  G11B2020/1222 ,  G11B2020/1267 ,  G11B2220/2541 ,  G11B2220/2575

摘要： An object of this invention is to provide an optical disc controller and an optical disc drive system which reduce the proceeding time for supplementing data that is deficient at the time of writing to the optical disc. The present invention relates to an optical disc controller and a optical disc drive system. An optical disc controller includes an interface circuit, a buffer, a memory manager, an ECC circuit, a modulation circuit, and an operation processor. The memory manager has a control register part, a copy transfer controller, and a buffer controller. The control register part further includes a copy sector number setting register for taking out and holding information of plural sector numbers of deficient data from a control signal of the operation processor. The copy transfer controller successively conducts copy transfer process for plural sector numbers based on the sector number information.

摘要翻译： 本发明的目的是提供一种光盘控制器和光盘驱动器系统，其减少了在写入光盘时补充不足的数据的进行时间。 本发明涉及光盘控制器和光盘驱动系统。 光盘控制器包括接口电路，缓冲器，存储器管理器，ECC电路，调制电路和操作处理器。 存储器管理器具有控制寄存器部分，拷贝传送控制器和缓冲器控制器。 控制寄存器部分还包括复制扇区号设置寄存器，用于从操作处理器的控制信号取出并保存多个扇区号不足数据的信息。 复制传送控制器基于扇区号信息连续进行多个扇区号的复制传送处理。

公开(公告)号：US06587916B2

公开(公告)日：2003-07-01

申请号：US09948042

申请日：2001-09-07

申请人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

发明人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

IPC分类号： G06F1300

CPC分类号： G06F15/7814

摘要： A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed. As a result, a layout area of an automatic sequence circuit is decreased, and a change in a sequence is also facilitated.

公开(公告)号：US5630172A

公开(公告)日：1997-05-13

申请号：US557987

申请日：1995-11-13

申请人： Yasuhiro Ami ,  Takeshi Fujii

发明人： Yasuhiro Ami ,  Takeshi Fujii

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/362

摘要： To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

摘要翻译： 为了在包含DMA传输电路的数据处理系统中改变DMA传输电路和总线使用CPU的优先顺序，当在DMA传送期间在DMA传送定时器中发生溢出时，用于使总线使用 直接从DMA传输电路到CPU被输出到总线使用权决定电路以暂停DMA传输。 总线使用权从DMA传输电路传输到CPU后，CPU恢复运行。 当DMA传输定时器发生溢出时，将总线使用权从CPU转移到DMA传输电路的请求信号被输出到总线使用权决定电路，以将总线使用权从CPU传输到DMA传输电路 与DMA传输开始的方式相同，并恢复DMA传输。

公开(公告)号：US5535362A

公开(公告)日：1996-07-09

申请号：US13450

申请日：1993-02-04

申请人： Yasuhiro Ami ,  Takeshi Fujii

发明人： Yasuhiro Ami ,  Takeshi Fujii

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/362

摘要： To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

摘要翻译： 为了在包含DMA传输电路的数据处理系统中改变DMA传输电路和总线使用CPU的优先顺序，当在DMA传送期间在DMA传送定时器中发生溢出时，用于使总线使用 直接从DMA传输电路到CPU被输出到总线使用权决定电路以暂停DMA传输。 总线使用权从DMA传输电路传输到CPU后，CPU恢复运行。 当DMA传输定时器发生溢出时，将总线使用权从CPU转移到DMA传输电路的请求信号被输出到总线使用权决定电路，以将总线使用权从CPU传输到DMA传输电路 与DMA传输开始的方式相同，并恢复DMA传输。