公开(公告)号：US06587916B2

公开(公告)日：2003-07-01

申请号：US09948042

申请日：2001-09-07

申请人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

发明人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

IPC分类号： G06F1300

CPC分类号： G06F15/7814

摘要： A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed. As a result, a layout area of an automatic sequence circuit is decreased, and a change in a sequence is also facilitated.

公开(公告)号：US06459640B1

公开(公告)日：2002-10-01

申请号：US09931243

申请日：2001-08-17

申请人： Kunio Tani ,  Tomohisa Iba ,  Tetsu Tashiro ,  Katsunobu Hongo ,  Tsutomu Tanaka ,  Mikio Kamiya ,  Toshihiro Sezaki ,  Hiroyuki Kimura

发明人： Kunio Tani ,  Tomohisa Iba ,  Tetsu Tashiro ,  Katsunobu Hongo ,  Tsutomu Tanaka ,  Mikio Kamiya ,  Toshihiro Sezaki ,  Hiroyuki Kimura

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/22

摘要： A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor. Thus a selecting device other than a laser can be applied for suppressing the increase of an LSI circuit size in the same chip as that for a dedicated control circuit, verifying the disconnected state of a FUSE circuit in the memory, and trimming the FUSE circuit.

摘要翻译： 非易失性半导体存储器包括由具有以矩阵形式布置的多个存储单元的存储器阵列组成的存储块，每个存储单元由非易失性晶体管构成; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的存储器解码器; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的电荷泵; 具有用于控制分配给寄存器1位的存储器解码器和电荷泵的多个控制信号中的每一个的寄存器; 以及更新装置，用于通过耦合到所述寄存器的数据处理器来更新所述寄存器的内容。 通过使用该更新装置来更新寄存器的内容，对存储器解码器和电荷泵进行控制，擦除存储块的数据，并且从非易失性晶体管写入/读取数据。 因此，可以应用激光以外的选择装置来抑制与专用控制电路相同的芯片中的LSI电路尺寸的增加，验证存储器中的FUSE电路的断开状态以及修整FUSE电路。

公开(公告)号：US06356480B1

公开(公告)日：2002-03-12

申请号：US09588645

申请日：2000-06-07

申请人： Kiyohiko Sakakibara ,  Susumu Takeuchi ,  Makoto Yamamoto ,  Kunio Tani ,  Yukio Nakamoto ,  Tomohisa Iba

发明人： Kiyohiko Sakakibara ,  Susumu Takeuchi ,  Makoto Yamamoto ,  Kunio Tani ,  Yukio Nakamoto ,  Tomohisa Iba

IPC分类号： G11C1606

CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

摘要： A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

摘要翻译： 非易失性半导体存储器件在字线处于非选择状态时选择位线，并且在所选择的位线上自选择地只读取过渡状态的单元。 非易失性半导体存储器件在完成擦除验证之后执行该回写操作。 此时，鉴于存储单元晶体管的截止状态漏电流来设定定义存储单元阈值的感测电流放大器的当前灵敏度。

公开(公告)号：US06466484B2

公开(公告)日：2002-10-15

申请号：US10056107

申请日：2002-01-28

申请人： Kiyohiko Sakakibara ,  Susumu Takeuchi ,  Makoto Yamamoto ,  Kunio Tani ,  Yukio Nakamoto ,  Tomohisa Iba

发明人： Kiyohiko Sakakibara ,  Susumu Takeuchi ,  Makoto Yamamoto ,  Kunio Tani ,  Yukio Nakamoto ,  Tomohisa Iba

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

摘要： A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

公开(公告)号：US20080225592A1

公开(公告)日：2008-09-18

申请号：US12073834

申请日：2008-03-11

申请人： Yasuhiko Taito ,  Naoki Otani ,  Tomohisa Iba ,  Tsukasa Oishi

发明人： Yasuhiko Taito ,  Naoki Otani ,  Tomohisa Iba ,  Tsukasa Oishi

IPC分类号： G11C5/02

CPC分类号： G11C16/16 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be erased, a voltage of the P-type well is applied to all word lines of a memory block to be not erased. Consequently, the voltage of the P-type well and the voltage of all word lines of the memory block to be not erased change at the same time. With this, it is possible to prevent a threshold voltage for the memory block to be not erased from changing.

摘要翻译： 利用该闪速存储器，由于在单个P型阱的表面上形成多个存储块，因此可以使布局区域变小。 此外，当擦除要擦除的存储块的数据时，P型阱的电压被施加到存储块的所有字线以便不被擦除。 因此，P型阱的电压和不被擦除的存储器块的所有字线的电压同时变化。 由此，可以防止存储块的阈值电压不被擦除。

公开(公告)号：US07630242B2

公开(公告)日：2009-12-08

申请号：US12073834

申请日：2008-03-11

申请人： Yasuhiko Taito ,  Naoki Otani ,  Tomohisa Iba ,  Tsukasa Oishi

发明人： Yasuhiko Taito ,  Naoki Otani ,  Tomohisa Iba ,  Tsukasa Oishi

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： With this flash memory, because a plurality of memory blocks are formed on a surface of a single P-type well, a layout area can be made small. Further, when erasing data for a memory block to be erased, a voltage of the P-type well is applied to all word lines of a memory block to be not erased. Consequently, the voltage of the P-type well and the voltage of all word lines of the memory block to be not erased change at the same time. With this, it is possible to prevent a threshold voltage for the memory block to be not erased from changing.

摘要翻译： 利用该闪速存储器，由于在单个P型阱的表面上形成多个存储块，因此可以使布局区域变小。 此外，当擦除要擦除的存储块的数据时，P型阱的电压被施加到存储块的所有字线以便不被擦除。 因此，P型阱的电压和不被擦除的存储器块的所有字线的电压同时变化。 由此，可以防止存储块的阈值电压不被擦除。

公开(公告)号：US5581510A

公开(公告)日：1996-12-03

申请号：US463804

申请日：1995-06-05

申请人： Tatsuki Furusho ,  Tomohisa Iba

发明人： Tatsuki Furusho ,  Tomohisa Iba

IPC分类号： G01R31/28 ,  G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/66 ,  G11C7/00 ,  G01R31/26 ,  G11C11/34

CPC分类号： G11C29/50 ,  G11C16/04

摘要： According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

摘要翻译： 根据编程操作所需的时间，相应的闪速存储器芯片被分成第一组和第二组芯片，其需要比用于编程操作的第一组时间更长的时间，以及后期测试，高温测试 同时对属于第一组的多个芯片进行低温测试，同时对属于第二组的多个芯片进行低温测试。