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    Microcomputer with built-in programmable nonvolatile memory
    1.
    发明授权
    Microcomputer with built-in programmable nonvolatile memory 有权

    公开(公告)号：US06587916B2

    公开(公告)日：2003-07-01

    申请号：US09948042

    申请日：2001-09-07

    申请人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

    发明人： Katsunobu Hongo ,  Tsutomu Tanaka ,  Toshihiro Sezaki ,  Hiroyuki Kimura ,  Mikio Kamiya ,  Yasuhiro Ami ,  Kunio Tani ,  Tomohisa Iba

    IPC分类号： G06F1300

    CPC分类号： G06F15/7814

    摘要： A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed. As a result, a layout area of an automatic sequence circuit is decreased, and a change in a sequence is also facilitated.

    Nonvolatile semiconductor memory and automatic erasing/writing method thereof
    2.
    发明授权
    Nonvolatile semiconductor memory and automatic erasing/writing method thereof 有权
    非易失性半导体存储器及其自动擦除/写入方法

    公开(公告)号：US06459640B1

    公开(公告)日：2002-10-01

    申请号：US09931243

    申请日：2001-08-17

    申请人： Kunio Tani ,  Tomohisa Iba ,  Tetsu Tashiro ,  Katsunobu Hongo ,  Tsutomu Tanaka ,  Mikio Kamiya ,  Toshihiro Sezaki ,  Hiroyuki Kimura

    发明人： Kunio Tani ,  Tomohisa Iba ,  Tetsu Tashiro ,  Katsunobu Hongo ,  Tsutomu Tanaka ,  Mikio Kamiya ,  Toshihiro Sezaki ,  Hiroyuki Kimura

    IPC分类号： G11C700

    CPC分类号： G11C29/846 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/22

    摘要： A nonvolatile semiconductor memory includes a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and an updating device for updating a content of the register by a data processor coupled to the register. By using this updating device to update the content of the register, the memory decoder and the charge pump are controlled, the data of the memory block is erased, and data is written in/read from the nonvolatile transistor. Thus a selecting device other than a laser can be applied for suppressing the increase of an LSI circuit size in the same chip as that for a dedicated control circuit, verifying the disconnected state of a FUSE circuit in the memory, and trimming the FUSE circuit.

    摘要翻译： 非易失性半导体存储器包括由具有以矩阵形式布置的多个存储单元的存储器阵列组成的存储块，每个存储单元由非易失性晶体管构成; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的存储器解码器; 用于擦除/写入/读取存储器阵列中的非易失性晶体管的数据所需的电荷泵; 具有用于控制分配给寄存器1位的存储器解码器和电荷泵的多个控制信号中的每一个的寄存器; 以及更新装置，用于通过耦合到所述寄存器的数据处理器来更新所述寄存器的内容。 通过使用该更新装置来更新寄存器的内容，对存储器解码器和电荷泵进行控制，擦除存储块的数据，并且从非易失性晶体管写入/读取数据。 因此，可以应用激光以外的选择装置来抑制与专用控制电路相同的芯片中的LSI电路尺寸的增加，验证存储器中的FUSE电路的断开状态以及修整FUSE电路。

    Planographic printing plate material
    7.
    发明授权
    Planographic printing plate material 有权
    平版印刷材料

    公开(公告)号：US07534551B2

    公开(公告)日：2009-05-19

    申请号：US11668611

    申请日：2007-01-30

    申请人： Kunio Tani

    发明人： Kunio Tani

    IPC分类号： G03F7/027 ,  G03F7/032 ,  B41N1/14 ,  G03F7/033

    CPC分类号： G03F7/033 ,  Y10S430/111

    摘要： An objective is to provide a planographic printing plate material exhibiting excellent developability, printing durability, together with excellent oxygen-shielding layer adhesion and moisture dependence after exposure. Disclosed is a planographic printing plate material possessing a support provided thereon, a photosensitive layer, wherein the photosensitive layer comprises (A) at least two binder polymers comprising different glass transition points (Tg) from each other, (B) a polymerizable ethylenic double bond-containing compound, and (C) a photopolymerization initiator.

    摘要翻译： 目的是提供一种平版印刷版材料，其具有优异的显影性，印刷耐久性，以及曝光后优异的氧气屏蔽层粘附性和水分依赖性。 公开了一种在其上设置有支撑体的平版印刷版材料，感光层，其中感光层包含（A）至少两种包含彼此不同的玻璃化转变点（Tg）的粘合剂聚合物，（B）可聚合的烯属双键 （C）光聚合引发剂。

    Light sensitive planographic printing plate material
    8.
    发明申请
    Light sensitive planographic printing plate material 审中-公开
    光敏平版印刷版材

    公开(公告)号：US20080038667A1

    公开(公告)日：2008-02-14

    申请号：US11881110

    申请日：2007-07-25

    申请人： Kunio Tani ,  Toshiyuki Matsumura

    发明人： Kunio Tani ,  Toshiyuki Matsumura

    IPC分类号： G03C1/00

    CPC分类号： G03F7/031 ,  G03F7/027

    摘要： Disclosed is a light sensitive planographic printing plate material comprising a support and provided thereon, a light sensitive layer containing a polymerization initiator, a polymerizable ethylenically unsaturated compound, a polymeric binder, and a sensitizing dye, wherein the polymerization initiator is a biimidazole compound, and the sensitizing dye is represented by formula (1),

    摘要翻译： 公开了一种光敏平版印刷版材料，其包含载体，其上设有含有聚合引发剂的光敏层，可聚合烯属不饱和化合物，聚合物粘合剂和增感染料，其中聚合引发剂是联咪唑化合物，和 敏化染料由式（1）表示，

    Data processor that utilizes full data width when processing a string operation
    9.
    发明授权
    Data processor that utilizes full data width when processing a string operation 失效
    在处理字符串操作时利用完整数据宽度的数据处理器

    公开(公告)号：US5497468A

    公开(公告)日：1996-03-05

    申请号：US327823

    申请日：1994-10-20

    申请人： Kunio Tani ,  Toyohiko Yoshida ,  Yukari Takata

    发明人： Kunio Tani ,  Toyohiko Yoshida ,  Yukari Takata

    IPC分类号： G06F7/00 ,  G06F7/02 ,  G06F9/30 ,  G06F9/305 ,  G06F9/315 ,  G06F17/30 ,  G06F7/66 ,  G06F7/20 ,  G06F7/38 ,  G06F9/00

    CPC分类号： G06F7/026 ,  G06F17/30985 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30167

    摘要： A data processor which performs in parallel a comparison process of n (which is an integer 2 or more)--sets first size data a elements by logical add operation between data elements in executing a first instruction for processing simultaneously number of n first size data elements, and performs a comparison process of one-set second size data elements by logical product operation of the compared results of whole data elements in executing a second instruction for processing individually second size data elements whose size is n times of said first size.

    摘要翻译： 在n（其为整数2以上）的比较处理中并行执行的数据处理器通过在执行用于同时处理n个第一大小数据元素的数量的第一指令的数据元素之间的逻辑添加操作来对元素进行第一大小数据 ，并且通过执行用于处理大小为所述第一尺寸的n倍的第二尺寸数据元素的第二指令，通过整个数据元素的比较结果的逻辑积运算来执行一组第二尺寸数据元素的比较处理。