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公开(公告)号：US20050096888A1
公开(公告)日：2005-05-05
申请号：US10924292
申请日：2004-08-23
Applicant: Yehea Ismail
Inventor： Yehea Ismail
CPC classification number: G06F17/504
Abstract: A method for mapping moments in a reduced order system of approximation order q for use in simulating a circuit or system having n state variables at n nodes, the circuit or system having I inputs. The method includes calculating only q+I moments, where q is the approximation order and I is the number of inputs of the circuit or system being simulated, sorting the state variables at the n nodes, selecting q nodes of the n nodes, and calculating the dominate poles and zeros using a multi-point moment matching algorithm to simultaneously match q+I moments at the selected q nodes of the circuit or system. In one embodiment, the method includes using extra dummy inputs such that the total number of inputs equals I, such that K*I>q where K is a constant having a value in the range of about 4 to 8.
Abstract translation: 用于在逼近阶数q的简化系统中映射矩的方法，用于模拟在n个节点处具有n个状态变量的电路或系统，该电路或系统具有I个输入。 该方法包括仅计算q + I矩，其中q是近似阶数，I是正在仿真的电路或系统的输入数，对n个节点进行状态变量排序，选择n个节点的q个节点，并计算 使用多点时刻匹配算法的主导极和零，以同时匹配电路或系统的所选q个节点处的q + I时刻。 在一个实施例中，该方法包括使用额外的虚拟输入，使得输入的总数等于I，使得K * I> q其中K是具有在大约4至8的范围内的值的常数。
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公开(公告)号：US08321304B2
公开(公告)日：2012-11-27
申请号：US12186637
申请日：2008-08-06
Applicant: Farrukh Khan , Yehea Ismail
Inventor： Farrukh Khan , Yehea Ismail
IPC: G06Q10/00
CPC classification number: G06Q10/087
Abstract: A stocked product sensing system that can be used with a product display, displaying product items on one or more shelves thereof, to determine the level of product availability and/or configuration of product items on one or more shelves of the product display. According to one embodiment of this invention, the stocked product sensing system utilizes capacitive sensing at the shelf-level. According to another embodiment of this invention, the stocked product sensing system utilizes optical sensing at the shelf-level. The stocked product sensing system of this invention may utilize a store-level management system and/or a central management system and generate low stock alarms based on user-defined criteria in a software system.
Abstract translation: 储存产品感测系统，其可以与产品显示器一起使用，在其一个或多个货架上显示产品，以确定在产品显示器的一个或多个货架上的产品可用性和/或配置的水平。 根据本发明的一个实施例，储备产品感测系统在货架级利用电容感测。 根据本发明的另一个实施例，库存产品感测系统在货架级利用光学感测。 本发明的储备产品感测系统可以利用商店级管理系统和/或中央管理系统，并且基于软件系统中的用户定义的标准生成低库存报警。
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Patent Agency Ranking
公开(公告)号：US20100036754A1
公开(公告)日：2010-02-11
申请号：US12186637
申请日：2008-08-06
Applicant: Farrukh Khan , Yehea Ismail
Inventor： Farrukh Khan , Yehea Ismail
CPC classification number: G06Q10/087
Abstract: A stocked product sensing system that can be used with a product display, displaying product items on one or more shelves thereof, to determine the level of product availability and/or configuration of product items on one or more shelves of the product display. According to one embodiment of this invention, the stocked product sensing system utilizes capacitive sensing at the shelf-level. According to another embodiment of this invention, the stocked product sensing system utilizes optical sensing at the shelf-level. The stocked product sensing system of this invention may utilize a store-level management system and/or a central management system and generate low stock alarms based on user-defined criteria in a software system.
Abstract translation: 储存产品感测系统，其可以与产品显示器一起使用，在其一个或多个货架上显示产品，以确定在产品显示器的一个或多个货架上的产品可用性和/或配置的水平。 根据本发明的一个实施例，储备产品感测系统在货架级利用电容感测。 根据本发明的另一个实施例，库存产品感测系统在货架级利用光学感测。 本发明的储备产品感测系统可以利用商店级管理系统和/或中央管理系统，并且基于软件系统中的用户定义的标准生成低库存报警。
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公开(公告)号：US06460165B1
公开(公告)日：2002-10-01
申请号：US09521178
申请日：2000-03-08
Applicant: Yehea Ismail , Eby G. Friedman
Inventor： Yehea Ismail , Eby G. Friedman
IPC: G06F1750
CPC classification number: G06F17/5036
Abstract: Transfer functions are calculated in the following manner within an RLC tree having a input and a plurality of nodes. The RLC tree is divided into left and right sub-trees joined by the node closest to the input. Each of the left and right sub-trees is divided into left and right sub-trees joined by a node. The sub-trees are divided recursively into still smaller sub-trees until the RLC tree is completely decomposed into left and right sub-trees joined by nodes. At each node of the RLC tree, the numerator and denominator of the transfer function at that node are determined in accordance with the left and right sub-trees joined by that node. The denominator of the transfer function of the node closest to the input is taken to be the denominator of all of the transfer functions of the RLC tree. For each node, the numerators of the transfer functions of the left and right sub-trees joined at that node are corrected in accordance with the denominators of the transfer functions of the left and right sub-trees joined at that node.
Abstract translation: 在具有输入和多个节点的RLC树中，以下列方式计算传递函数。 RLC树被划分为最靠近输入的节点连接的左和右子树。 左和右子树中的每一个被分为由节点连接的左和右子树。 子树被递归地分割成更小的子树，直到RLC树被完全分解成由节点连接的左和右子树。 在RLC树的每个节点处，根据由该节点连接的左和右子树确定该节点处的传递函数的分子和分母。 最接近输入的节点的传递函数的分母被认为是RLC树的所有传递函数的分母。 对于每个节点，在该节点处连接的左和右子树的传递函数的分子根据在该节点处连接的左和右子树的传递函数的分母来校正。
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公开(公告)号：US20090119037A1
公开(公告)日：2009-05-07
申请号：US12267472
申请日：2008-11-07
Applicant: DiaaEldin Khalil , Yehea Ismail , Debjit Sinha , Hai Zhou
Inventor： DiaaEldin Khalil , Yehea Ismail , Debjit Sinha , Hai Zhou
CPC classification number: G06F17/5036 , G01R21/00 , G01R31/31721 , G06F2217/78
Abstract: A method for dynamic timing-dependent power estimation for a digital circuit having coupled interconnects and at least two gates. In one embodiment, the method includes the steps of capturing information on relative switching activities and timing dependence for the coupled interconnects in the digital circuit, estimating the probabilities associated with switching activities and timing dependence for each gate in the digital circuit from the captured information, and obtaining dynamic power estimation of the digital circuit from the estimations of the probabilities.
Abstract translation: 一种用于具有耦合互连和至少两个门的数字电路的动态时序相关功率估计的方法。 在一个实施例中，该方法包括以下步骤：捕获关于数字电路中的耦合互连的相对切换活动和时序相关性的信息，从捕获的信息中估计与数字电路中每个门的切换活动和定时相关性的概率， 并从概率的估计中获得数字电路的动态功率估计。
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6.发明申请公开(公告)号：US20080120514A1
公开(公告)日：2008-05-22
申请号：US11938040
申请日：2007-11-09
Applicant: Yehea Ismail , Gokhan Memik , Ja Chun Ku , Serkan Ozdemir
Inventor： Yehea Ismail , Gokhan Memik , Ja Chun Ku , Serkan Ozdemir
IPC: G06F1/00
CPC classification number: G06F1/32 , G06F1/3275 , H01L23/34 , H01L23/42 , H01L2924/0002 , Y02D10/14 , Y02D50/20 , H01L2924/00
Abstract: Certain embodiments provide systems and methods for reducing power consumption in on-chip caches. Certain embodiments include Power Density-Minimized Architecture (PMA) and Block Permutation Scheme (BPS) for thermal management of on-chip caches. Instead of turning off entire banks, PMA architecture spreads out active parts in a cache bank by turning off alternating rows in a bank. This reduces the power density of the active parts in the cache, which then lowers the junction temperature. The drop in the temperature results in energy savings from the remaining active parts of the cache. BPS aims to maximize the physical distance between the logically consecutive blocks of the cache. Since there is spatial locality in caches, this distribution results in an increase in the distance between hot spots, thereby reducing the peak temperature. The drop in the peak temperature then results in a leakage power reduction in the cache.
Abstract translation: 某些实施例提供用于降低片上高速缓存中的功耗的系统和方法。 某些实施例包括用于片上高速缓存的热管理的功率密度最小化架构（PMA）和块置换方案（BPS）。 PMA架构不是关闭整个银行，而是通过关闭银行中的交替行来扩展缓存库中的活动部分。 这降低了高速缓存中活动部件的功率密度，从而降低了结温。 温度的降低导致缓存的剩余活动部分的能量节省。 BPS旨在最大化缓存的逻辑连续块之间的物理距离。 由于缓存中存在空间局部性，所以这种分布导致热点之间的距离增加，从而降低峰值温度。 然后，峰值温度的下降导致高速缓存中的泄漏功率降低。
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公开(公告)号：US20050225459A1
公开(公告)日：2005-10-13
申请号：US10813084
申请日：2004-03-31
Applicant: Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehea Ismail
Inventor： Maged Ghoneima , Peter Caputa , Muhammad Khellah , Ram Krishnamurthy , James Tschanz , Yibin Ye , Vivek De , Yehea Ismail
CPC classification number: G06F13/4072 , Y02D10/14 , Y02D10/151
Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。
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