公开(公告)号：US06535040B2

公开(公告)日：2003-03-18

申请号：US09929522

申请日：2001-08-14

申请人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

发明人： Yeon-jae Jung ,  Chang-sik Yoo ,  Kee-wook Jung ,  Won-chan Kim

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

摘要翻译： 占空比校正电路包括占空比校正器和检测电路。 占空比校正器响应于第一检测信号和具有第一占空比的第一控制信号产生具有比第一占空比更高的等效程度的第二占空比的第一输入信号。 检测电路响应于第一输入信号产生第一检测信号。 检测电路包括具有第一和第二电流源的电流源和电耦合到第一和第二电流源的偏置电路，并响应于第一输入信号控制第一和第二电流源的偏置。

公开(公告)号：US06385126B2

公开(公告)日：2002-05-07

申请号：US09757792

申请日：2001-01-11

申请人： Yeon-jae Jung ,  Seung-wook Lee ,  Dae-yun Shim ,  Won-chan Kim

发明人： Yeon-jae Jung ,  Seung-wook Lee ,  Dae-yun Shim ,  Won-chan Kim

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G06F1/12 ,  G11C7/22 ,  G11C11/4076 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0893

摘要： A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

摘要翻译： 提供时钟同步电路，用于使外部时钟信号与内部时钟信号同步。 该电路连接到适于输出内部时钟信号的时钟缓冲器。 该电路包括适于接收外部时钟信号并输出​​其间具有预定相位差的多个参考时钟信号的第一回路。 第二环路适于延迟多个参考时钟信号; 从所述多个延迟参考时钟信号中选择信号; 将选择的信号提供给时钟缓冲器; 检测从时钟缓冲器输出的内部时钟信号与外部时钟信号之间的相位差; 产生多个控制电压以减小检测到的相位差，并且响应于多个控制电压来控制多个参考时钟信号中的每一个的延迟量; 以使内部时钟信号与外部时钟信号同步。