公开(公告)号：US20050035459A1

公开(公告)日：2005-02-17

申请号：US10946675

申请日：2004-09-22

申请人： Kathleen Yu ,  Kirk Strozewski ,  Janos Farkas ,  Hector Sanchez ,  Yeong-Jyh Lii

发明人： Kathleen Yu ,  Kirk Strozewski ,  Janos Farkas ,  Hector Sanchez ,  Yeong-Jyh Lii

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L21/4763 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L23/5283 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

摘要翻译： 导线的厚度变化，有助于克服RC延迟和噪声耦合。 通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。 通过将介电层蚀刻成不同的厚度来实现导体深度变化。 电介质层上的不同厚度的导电填充导致厚度变化的导线。 在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。 为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

公开(公告)号：US06287951B1

公开(公告)日：2001-09-11

申请号：US09206715

申请日：1998-12-07

申请人： Kevin D. Lucas ,  Christopher D. Pettinato ,  Wayne D. Clark ,  Stanley M. Filipiak ,  Yeong Jyh Lii

发明人： Kevin D. Lucas ,  Christopher D. Pettinato ,  Wayne D. Clark ,  Stanley M. Filipiak ,  Yeong Jyh Lii

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895

摘要： A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.

摘要翻译： 在绝缘层（26,24,22和20）上形成硬掩模层（34），并且形成覆盖在硬掩模层（34）上的抗反射层（36）。 在抗反射层（36）上形成抗蚀剂层（38），在抗蚀剂层上形成开口以露出抗反射层（36）的表面部分。 对抗反射层（36）的暴露表面部分和硬掩模层（34）的部分进行蚀刻以暴露绝缘层（26,24,22和20）的表面部分，形成特征开口（61） 在绝缘层（26,24,22和20）中。 沉积导电材料（74）以填充特征开口（61），并且去除位于开口外侧的导电材料（74）的部分。