公开(公告)号：US20070195654A1

公开(公告)日：2007-08-23

申请号：US11307779

申请日：2006-02-22

申请人： Yeow-Chyi Chen

发明人： Yeow-Chyi Chen

IPC分类号： G11B21/08

CPC分类号： G11B20/10527 ,  G11B27/105 ,  G11B2020/10768 ,  G11B2020/1287 ,  G11B2220/2537

摘要： A buffer control system for generating a buffered signal having reduced buffer delay time between playback of tracks includes a controller module for providing an end target and for selection of a servo data signal corresponding to a desired track; a compare circuit coupled to the servo data signal for comparing a timestamp of the servo data signal to the end target, and asserting an end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit for storing the servo data signal as stored data to fill a capacity of an internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level; wherein the controller module is for updating selection of the servo data signal according to a next desired track upon assertion of the end match signal.

摘要翻译： 用于产生缓冲信号的缓冲器控制系统，其具有在轨道重放之间具有减小的缓冲延迟时间的缓冲器控制系统，该控制器模块用于提供结束目标并用于选择对应于所需轨道的伺服数据信号; 耦合到所述伺服数据信号的比较电路，用于将所述伺服数据信号的时间戳与所述结束目标进行比较，以及当所述伺服数据信号的所述时间戳与所述结束目标匹配时，断言结束匹配信号; 以及数据缓冲单元，用于存储伺服数据信号作为存储数据以填充内部存储器的容量，并且当容量已经达到预定水平时，从存储的数据流出缓冲信号; 其中所述控制器模块用于在断言所述结束匹配信号时，根据下一所需轨迹来更新所述伺服数据信号的选择。

公开(公告)号：US20100332734A1

公开(公告)日：2010-12-30

申请号：US12721724

申请日：2010-03-11

申请人： Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

发明人： Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F13/1684 ,  Y02D10/14

摘要： A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

摘要翻译： 闪存器件包括存储器阵列和存储器控制电路。 存储器阵列包括存储器模块。 每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。 存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

公开(公告)号：US08447917B2

公开(公告)日：2013-05-21

申请号：US12721724

申请日：2010-03-11

申请人： Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

发明人： Yeow-Chyi Chen ,  Hong-Ching Chen ,  Li-Chun Tu ,  Tzu-Chieh Lin ,  Chi-Wei Peng

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F13/1684 ,  Y02D10/14

摘要： A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

摘要翻译： 闪存器件包括存储器阵列和存储器控制电路。 存储器阵列包括存储器模块。 每个存储器模块位于存储器通道中并且包括预定数量的存储器单元。 存储器控制电路通过地址锁存使能（ALE）引脚和命令锁存使能（CLE）引脚耦合到存储器阵列。 ALE引脚和CLE引脚耦合到所有存储单元，并由存储器阵列中的所有存储单元共享。

公开(公告)号：US20090327750A1

公开(公告)日：2009-12-31

申请号：US12164097

申请日：2008-06-29

申请人： Tse-Hong Wu ,  Yao-Dun Chang ,  Wan-Perng Lin ,  Yeow-Chyi Chen ,  Yung-Sheng Chiu

发明人： Tse-Hong Wu ,  Yao-Dun Chang ,  Wan-Perng Lin ,  Yeow-Chyi Chen ,  Yung-Sheng Chiu

IPC分类号： H04L9/06

CPC分类号： G06F12/1408 ,  G06F12/1416 ,  G06F21/79 ,  G06F2221/2105

摘要： A security system for code dump protection includes a storage device, a processor, and a decryption unit. The storage device has a protected storage area storing at least an encrypted code segment. The processor is utilized for issuing at least one address pattern to the storage device for obtaining at least one information pattern corresponding to the address pattern. The decryption unit checks signal communicated between the processor and the storage device to generate a check result, and determines whether to decrypt the encrypted code segment in the protected storage area to generate a decrypted code segment to the processor according to the check result.

摘要翻译： 用于代码转储保护的安全系统包括存储设备，处理器和解密单元。 存储设备具有至少存储加密代码段的保护存储区域。 处理器被用于向存储设备发出至少一个地址模式，以获得对应于地址模式的至少一个信息模式。 解密单元检查在处理器和存储设备之间传送的信号以产生检查结果，并且确定是否解密受保护存储区域中的加密代码段，以根据检查结果向处理器产生解密的代码段。

公开(公告)号：US08199618B2

公开(公告)日：2012-06-12

申请号：US11307779

申请日：2006-02-22

申请人： Yeow-Chyi Chen

发明人： Yeow-Chyi Chen

IPC分类号： G11B7/00

CPC分类号： G11B20/10527 ,  G11B27/105 ,  G11B2020/10768 ,  G11B2020/1287 ,  G11B2220/2537

摘要： A buffer control system for generating a buffered signal having reduced buffer delay time between playback of tracks includes a controller module for providing an end target and for selection of a servo data signal corresponding to a desired track; a compare circuit coupled to the servo data signal for comparing a timestamp of the servo data signal to the end target, and asserting an end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit for storing the servo data signal as stored data to fill a capacity of an internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level; wherein the controller module is for updating selection of the servo data signal according to a next desired track upon assertion of the end match signal.

摘要翻译： 用于产生缓冲信号的缓冲器控制系统，其具有在轨道重放之间具有减小的缓冲延迟时间的缓冲器控制系统，该控制器模块用于提供结束目标并用于选择对应于所需轨道的伺服数据信号; 耦合到所述伺服数据信号的比较电路，用于将所述伺服数据信号的时间戳与所述结束目标进行比较，以及当所述伺服数据信号的所述时间戳与所述结束目标匹配时，断言结束匹配信号; 以及数据缓冲单元，用于存储伺服数据信号作为存储数据以填充内部存储器的容量，并且当容量已经达到预定水平时，从存储的数据流出缓冲信号; 其中所述控制器模块用于在断言所述结束匹配信号时，根据下一所需轨迹来更新所述伺服数据信号的选择。

公开(公告)号：US20110010512A1

公开(公告)日：2011-01-13

申请号：US12500457

申请日：2009-07-09

申请人： Tzu-chieh Lin ,  Hong-ching Chen ,  Yeow-chyi Chen

发明人： Tzu-chieh Lin ,  Hong-ching Chen ,  Yeow-chyi Chen

IPC分类号： G06F12/00

CPC分类号： G06F13/4239

摘要： A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has at least one high priority cycle and at least one low priority cycle. When a low priority cycle is overlapped with a high priority cycle, the low priority cycle is suspended, and the high priority cycle is operated first. After the high priority cycle is finished, the suspended low priority cycle is then resumed. By doing so, the shared I/O bus may be used by one memory unit during a busy cycle for another memory unit, during which the latter memory unit does not use the I/O bus. Therefore, the I/O bus can be more efficiently used.

摘要翻译： 公开了一种使用该方法控制存储系统和存储系统的方法。 在存储系统中，至少两个存储器单元共享I / O总线。 共享I / O总线传送每个存储器单元的信息以执行操作。 该操作具有至少一个高优先级循环和至少一个低优先级循环。 当低优先级周期与高优先级周期重叠时，低优先级周期被暂停，并且首先操作高优先级循环。 高优先级循环结束后，恢复暂停的低优先级循环。 通过这样做，在另一个存储器单元的繁忙周期期间，一个存储器单元可以使用共享的I / O总线，在此期间，后一个存储器单元不使用I / O总线。 因此，可以更有效地使用I / O总线。

公开(公告)号：US20100096629A1

公开(公告)日：2010-04-22

申请号：US12254156

申请日：2008-10-20

申请人： Yeow Chyi CHEN

发明人： Yeow Chyi CHEN

IPC分类号： H01L25/065

CPC分类号： G11C29/32 ,  G11C5/04 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command.

摘要翻译： 本发明提供一种多芯片模块。 在一个实施例中，多芯片模块包括串行闪存管芯和主管芯，并且主管芯包括内置的自检控制器和串行闪存控制器。 内置的自检控制器产生一个写入命令，将第一个数据写入到串行闪存芯片的存储器位置，产生读取命令，从串行闪存芯片的存储单元读取第二个数据，并将第二个数据与 用于确定存储器位置是否有缺陷以产生关于串行闪存芯片的失败地址信息的第一数据。 串行闪存控制器根据写入命令和读取命令访问串行闪存芯片。