公开(公告)号：US20070146072A1

公开(公告)日：2007-06-28

申请号：US11604198

申请日：2006-11-27

申请人： Norikazu Ohta ,  Yoshie Ohira ,  Yasuaki Makino ,  Hiromi Ariyoshi

发明人： Norikazu Ohta ,  Yoshie Ohira ,  Yasuaki Makino ,  Hiromi Ariyoshi

IPC分类号： H03F3/45

CPC分类号： H03K3/354 ,  H03K3/0315 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00169

摘要： 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor. The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor when the lower transistor is turned on.

摘要翻译： 并联连接第n个第n个（n =奇数）对的第一个第一和第二个晶体管，每对晶体管具有串联连接的上部晶体管和下部晶体管 。 先前一对晶体管的上部晶体管和下部晶体管之间的点连接到后续晶体管的下部晶体管的栅极，并且上部晶体管和下部晶体管之间的点位于第n / >一对晶体管连接到第一下晶体管的栅极。 电容器插在下晶体管和直接电源之间。 连接到上部晶体管的栅极的电流调节电路，其中电流调节电路向每个上部晶体管的每个栅极提供栅极电压。 调整栅极电压的大小，使得由于栅极电压而在上部晶体管的源极和漏极之间流动的电流的大小与当下部晶体管为相应的下部晶体管的源极和栅极之间的电压成比例时 打开。

公开(公告)号：US07233136B2

公开(公告)日：2007-06-19

申请号：US11311182

申请日：2005-12-20

申请人： Yasuaki Makino ,  Norikazu Ohta ,  Yoshie Ohira ,  Hirofumi Funabashi

发明人： Yasuaki Makino ,  Norikazu Ohta ,  Yoshie Ohira ,  Hirofumi Funabashi

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/30

摘要： A reference voltage circuit includes an operational amplifier, a first fixed resistance resistor, a second fixed resistance resistor, a third fixed resistance resistor, a first diode and a second diode. The reference voltage circuit further includes a fourth fixed resistance resistor having an end connected to a non-inverting input terminal of the operational amplifier and the other end connected to the first diode. The reference voltage circuit is characterized by a value of the resistance of the fourth resistor being less than the resistance of the first resistor and a temperature coefficient of the fourth resistor being greater than any of the temperature coefficients of the first, second and third resistors.

摘要翻译： 参考电压电路包括运算放大器，第一固定电阻电阻，第二固定电阻电阻，第三固定电阻电阻，第一二极管和第二二极管。 参考电压电路还包括第四固定电阻电阻器，其端部连接到运算放大器的非反相输入端子，另一端连接到第一二极管。 参考电压电路的特征在于第四电阻器的电阻小于第一电阻器的电阻值，第四电阻器的温度系数大于第一，第二和第三电阻器的任何温度系数。

公开(公告)号：US07560998B2

公开(公告)日：2009-07-14

申请号：US11604198

申请日：2006-11-27

申请人： Norikazu Ohta ,  Yoshie Ohira ,  Yasuaki Makino ,  Hiromi Ariyoshi

发明人： Norikazu Ohta ,  Yoshie Ohira ,  Yasuaki Makino ,  Hiromi Ariyoshi

IPC分类号： H03K3/03 ,  H03L1/00

CPC分类号： H03K3/354 ,  H03K3/0315 ,  H03K2005/0013 ,  H03K2005/00143 ,  H03K2005/00169

摘要： 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor. The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor when the lower transistor is turned on.

摘要翻译： 第一至第n对晶体管（n =奇数）并联连接，并且每对晶体管具有串联连接的上晶体管和下晶体管。 前一对晶体管的上晶体管和下晶体管之间的点连接到后续晶体管的下晶体管的栅极，并且第n对晶体管的上晶体管和下晶体管之间的点连接到 第一低级晶体管的栅极。 电容器插在下晶体管和直接电源之间。 连接到上部晶体管的栅极的电流调节电路，其中电流调节电路向每个上部晶体管的每个栅极提供栅极电压。 调整栅极电压的大小，使得由于栅极电压而在上部晶体管的源极和漏极之间流动的电流的大小与当下部晶体管为相应的下部晶体管的源极和栅极之间的电压成比例时 打开。

公开(公告)号：US20060176043A1

公开(公告)日：2006-08-10

申请号：US11311182

申请日：2005-12-20

申请人： Yasuaki Makino ,  Norikazu Ohta ,  Yoshie Ohira ,  Hirofumi Funabashi

发明人： Yasuaki Makino ,  Norikazu Ohta ,  Yoshie Ohira ,  Hirofumi Funabashi

IPC分类号： G05F3/04 ,  G05F3/08

CPC分类号： G05F3/30

摘要： A reference voltage circuit includes an operational amplifier, a first fixed resistance resistor, a second fixed resistance resistor, a third fixed resistance resistor, a first diode and a second diode. The reference voltage circuit further includes a fourth fixed resistance resistor having an end connected to a non-inverting input terminal of the operational amplifier and the other end connected to the first diode. The reference voltage circuit is characterized by a value of the resistance of the fourth resistor being less than the resistance of the first resistor and a temperature coefficient of the fourth resistor being greater than any of the temperature coefficients of the first, second and third resistors.

摘要翻译： 参考电压电路包括运算放大器，第一固定电阻电阻，第二固定电阻电阻，第三固定电阻电阻，第一二极管和第二二极管。 参考电压电路还包括第四固定电阻电阻器，其端部连接到运算放大器的非反相输入端子，另一端连接到第一二极管。 参考电压电路的特征在于第四电阻器的电阻小于第一电阻器的电阻值，第四电阻器的温度系数大于第一，第二和第三电阻器的任何温度系数。