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1.发明申请公开(公告)号：US20100314771A1
公开(公告)日：2010-12-16
申请号：US12724051
申请日：2010-03-15
IPC分类号： H01L23/535
CPC分类号： H01L27/115 , G03F1/36 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first to third lines. The second line has a width equal to the first line. The second line is arranged with a space equal to the width from the first line, and partially has a gap. The third line is connected to one end of the first line and to a side of one end of the second line.
摘要翻译： 半导体器件包括第一至第三线。 第二行的宽度等于第一行。 第二线排列有与第一线宽度相等的空间，部分地具有间隙。 第三线连接到第一线的一端和第二线的一端的一侧。
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公开(公告)号：US20100232225A1
公开(公告)日：2010-09-16
申请号：US12723864
申请日：2010-03-15
申请人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
发明人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
CPC分类号： G11C8/10 , G11C16/26 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526
摘要： A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.
摘要翻译： 半导体存储装置具有读出放大器。 读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连，并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上互连件，并且连接到设置在所述第二上互连件下方的所述虚拟接触互连。
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公开(公告)号：US20080198667A1
公开(公告)日：2008-08-21
申请号：US12032206
申请日：2008-02-15
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：存储单元阵列，具有：具有串联连接的多个存储单元的单元串; 分别连接到所述多个存储单元的多个字线; 连接到单元串的一端的源极侧选择栅极; 和连接到电池串的另一端的漏极侧选择栅极; 字线选择器，其选择连接到要写入的目标存储器单元的字线之一; 以及在目标存储单元的数据写入之后均衡多个字线的电压的均衡单元结束。
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公开(公告)号：US08243524B2
公开(公告)日：2012-08-14
申请号：US12723864
申请日：2010-03-15
申请人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
发明人： Yuya Suzuki , Toshiki Hisada , Yoshikazu Hosomura
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C16/26 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526
摘要： A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.
摘要翻译： 半导体存储装置具有读出放大器。 读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连，并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上部互连件，并且连接到设置在所述第二上部互连件下方的所述虚拟接触互连件。
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公开(公告)号：US07646646B2
公开(公告)日：2010-01-12
申请号：US12032206
申请日：2008-02-15
CPC分类号： G11C16/3418
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：存储单元阵列，具有：具有串联连接的多个存储单元的单元串; 分别连接到所述多个存储单元的多个字线; 连接到单元串的一端的源极侧选择栅极; 和连接到电池串的另一端的漏极侧选择栅极; 字线选择器，其选择连接到要写入的目标存储器单元的字线之一; 以及在目标存储单元的数据写入之后均衡多个字线的电压的均衡单元结束。
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