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    Template for assisting cover design
    1.
    发明授权
    Template for assisting cover design 失效
    帮助封面设计的模板

    公开(公告)号：US07404257B2

    公开(公告)日：2008-07-29

    申请号：US11611451

    申请日：2006-12-15

    Applicant: Sheng-Feng Hung ,  Tzu-Cheng Yu ,  Yu-Chuan Liang ,  Chao Liu ,  Hong-Xiu Luo

    Inventor： Sheng-Feng Hung ,  Tzu-Cheng Yu ,  Yu-Chuan Liang ,  Chao Liu ,  Hong-Xiu Luo

    IPC: G01B5/28

    CPC classification number: B44C5/00

    Abstract: A template (10) for assisting cover design has a decorative surface (12). The decorative surface includes a curved portion (121) and an essentially flat portion (122) around the curved portion. The flat portion has a plurality of slots (124) formed therein and is divided into several sections by the slots. Each section has been processed to have a characteristic texture. Each texture within a given section is different from that of any other one of the sections.

    Abstract translation: 用于辅助盖设计的模板（10）具有装饰表面（12）。 装饰表面包括弯曲部分（121）和围绕弯曲部分的基本平坦部分（122）。 平坦部分具有形成在其中的多个狭槽（124），并且由狭槽分成几个部分。 每个部分都被处理成具有特征纹理。 给定部分内的每个纹理与任何其他部分的纹理不同。

    BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE
    7.
    发明申请
    BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE 审中-公开
    具有浮动基板的断电电压改进

    公开(公告)号：US20120126334A1

    公开(公告)日：2012-05-24

    申请号：US12953665

    申请日：2010-11-24

    Applicant: Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    Inventor： Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/78 ,  H01L27/0251

    Abstract: The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided.

    Abstract translation: 本公开提供一种半导体器件，其包括具有电阻元件区域和晶体管区域的衬底，衬底的电阻器元件区域中的浮置衬底，设置在浮置衬底上的外延层以及限定在外延层中的有源区 层，被隔离结构包围的活性区域。 该器件还包括设置在隔离结构上的电阻器块，以及设置在电阻器块，隔离结构和有源区域上的电介质层。 还提供了一种制造这种半导体器件的方法。

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