公开(公告)号：US08786050B2

公开(公告)日：2014-07-22

申请号：US13100714

申请日：2011-05-04

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L21/02

CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

公开(公告)号：US08704279B2

公开(公告)日：2014-04-22

申请号：US13481462

申请日：2012-05-25

申请人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/80

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

摘要翻译： 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08624322B1

公开(公告)日：2014-01-07

申请号：US13551262

申请日：2012-07-17

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

IPC分类号： H01L23/62 ,  H01L21/8234

CPC分类号： H01L27/0629

摘要： Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

摘要翻译： 提供高压半导体器件。 高电压半导体器件包括具有栅极，源极和漏极的晶体管。 源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。 栅极形成在漂移区域上以及源极和漏极之间。 晶体管被配置为处理至少几百伏特的高电压条件。 高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。 电介质结构突出进出基板。 电介质结构的不同部分具有不均匀的厚度。 高电压半导体器件包括在电介质结构上形成的电阻器。 电阻器具有大致均匀间隔开的多个绕组段。

公开(公告)号：US20130313617A1

公开(公告)日：2013-11-28

申请号：US13481462

申请日：2012-05-25

申请人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/80

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

摘要翻译： 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08664741B2

公开(公告)日：2014-03-04

申请号：US13160030

申请日：2011-06-14

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/02

CPC分类号： H01L29/0649 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/761 ,  H01L21/76202 ,  H01L23/528 ,  H01L27/0676 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/8605 ,  H01L29/868

摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

摘要翻译： 提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。 第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。 半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。 半导体器件包括形成在绝缘结构上的细长电阻器件。 电阻器件分别设置在电阻器件的相对端处的第一和第二部分。 半导体器件包括形成在电阻器件上的互连结构。 互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

公开(公告)号：US20120299096A1

公开(公告)日：2012-11-29

申请号：US13186660

申请日：2011-07-20

申请人： Ker Hsiao HUO ,  Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG

发明人： Ker Hsiao HUO ,  Ru-Yi SU ,  Fu-Chih YANG ,  Chun Lin TSAI ,  Chih-Chang CHENG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

摘要翻译： 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US20120126334A1

公开(公告)日：2012-05-24

申请号：US12953665

申请日：2010-11-24

申请人： Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Chia-Chin Shen ,  Yu Chuan Liang ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L27/0251

摘要： The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided.

摘要翻译： 本公开提供一种半导体器件，其包括具有电阻元件区域和晶体管区域的衬底，衬底的电阻器元件区域中的浮置衬底，设置在浮置衬底上的外延层以及限定在外延层中的有源区 层，被隔离结构包围的活性区域。 该器件还包括设置在隔离结构上的电阻器块，以及设置在电阻器块，隔离结构和有源区域上的电介质层。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US20110241114A1

公开(公告)日：2011-10-06

申请号：US12753486

申请日：2010-04-02

申请人： RU-YI SU ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Chia-Chin Shen ,  Eric Huang ,  Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

发明人： RU-YI SU ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Chia-Chin Shen ,  Eric Huang ,  Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Hsiao-Chin Tuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816

摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well.

摘要翻译： 在本公开中提供了高电压金属氧化物半导体横向扩散装置（HV LDMOS）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 第二井的一部分围绕源，第二井的另一部分从第一井的第一部分横向延伸。

公开(公告)号：US08803232B2

公开(公告)日：2014-08-12

申请号：US13186660

申请日：2011-07-20

申请人： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

发明人： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

摘要翻译： 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US08680616B2

公开(公告)日：2014-03-25

申请号：US12959538

申请日：2010-12-03

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L21/00

CPC分类号： H01L29/7816 ,  H01L21/76202 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/861

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中，并且具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。