Multi-element heat-resistant aluminum alloy material with high strength and preparation method thereof
    1.
    发明授权
    Multi-element heat-resistant aluminum alloy material with high strength and preparation method thereof 有权
    高强度多元耐热铝合金材料及其制备方法

    公开(公告)号:US08728256B2

    公开(公告)日:2014-05-20

    申请号:US13392868

    申请日:2010-08-04

    IPC分类号: C22F1/057 C22C21/12

    摘要: A heat-resistant aluminum alloy material with high strength and preparation method thereof are provided. The aluminum alloy material comprises (by weight %): Cu: 1.0˜10.0, Mn: 0.05˜1.5, Cd: 0.01˜0.5, Ti: 0.01˜0.5%, B: 0.01˜0.2 or C: 0.0001˜0.15, Zr: 0.01˜1.0, R: 0.001˜3 or (R1+R2): 0.001˜3, RE: 0.05˜5, and balance Al:, wherein, R, R1, and R2 include Be, Co, Cr, Li, Mo, Nb, Ni, W. The Al alloy has the advantages of narrow quasi-solid phases temperature range of alloys, low hot cracking liability during casting improved high temperature strength and high heat resistance.

    摘要翻译: 提供了具有高强度的耐热铝合金材料及其制备方法。 铝合金材料包含(重量%):Cu:1.0〜10.0,Mn:0.05〜1.5,Cd:0.01〜0.5,Ti:0.01〜0.5%,B:0.01〜0.2或C:0.0001〜0.15,Zr: 0.01〜1.0,R:0.001〜3或(R1 + R2):0.001〜3,RE:0.05〜5,余量为Al:其中,R,R1,R2包括Be,Co,Cr,Li,Mo, Nb,Ni,W。Al合金具有合金准相固态温度范围窄,铸造时低热裂纹性能提高耐高温强度和高耐热性的优点。

    Phase detector for a ternary signal
    2.
    发明授权
    Phase detector for a ternary signal 失效
    三相信号的相位检测器

    公开(公告)号:US5731719A

    公开(公告)日:1998-03-24

    申请号:US554512

    申请日:1995-11-07

    IPC分类号: H03K5/26 H03M5/16 H03K5/22

    CPC分类号: H03M5/16 H03K5/26

    摘要: A method and apparatus for recovering timing information from a ternary signal includes transforming a ternary signal into a binary signal while retaining the necessary timing information. A two facet circuit initially receives a ternary signal, one that includes three levels of values. A first facet of this circuit transforms the ternary signal into two binary signals, each having one of the three levels represented by one value and both having the same level represented by the other value. The second facet of this circuit combines the two binary signals to produce a third binary signal that has one value representing one level and another value representing the two other levels.

    摘要翻译: 用于从三元信号中恢复定时信息的方法和装置包括将三进制信号变换为二进制信号,同时保留必要的定时信息。 一个两面电路最初接收一个三元信号,一个包含三个电平值。 该电路的第一面将三进制信号变换为两个二进制信号,每个二进制信号具有由一个值表示的三个电平之一,并且两者具有由另一个值表示的相同电平。 该电路的第二面结合了两个二进制信号以产生具有代表一个电平的一个值和表示另外两个电平的另一个值的第三二进制信号。

    DEHYDRATION DEVICE
    3.
    发明申请
    DEHYDRATION DEVICE 审中-公开
    脱水装置

    公开(公告)号:US20120247453A1

    公开(公告)日:2012-10-04

    申请号:US13432134

    申请日:2012-03-28

    申请人: YUN-CHE WEN

    发明人: YUN-CHE WEN

    IPC分类号: F24J2/40

    摘要: A dehydration device includes a solar energy collection device connected with a water source so as to transfer solar energy into thermo energy which heats water that is supplied from the water source. A water storage device includes at least one hot water tank which has a heater connected to the solar energy collection device. The water heated by the solar energy collection device is stored in the at least one hot water tank. A heat-exchange device has a pipe connected with the water storage device, and an air delivery unit which blows air toward the pipe to form hot air to dehydrate foods. A windmill generates electric power which is provided to the dehydration device. The dehydration device uses green energy to dehydrate foods to keep proper freshness and nutrition. The dehydration device is easily moved and friendly to the environment.

    摘要翻译: 脱水装置包括与水源连接的太阳能收集装置,以将太阳能转移到热能中,加热从水源供应的水。 储水装置包括至少一个具有连接到太阳能收集装置的加热器的热水箱。 由太阳能收集装置加热的水储存在至少一个热水箱中。 热交换装置具有与储水装置连接的管道,以及将空气吹向管道以形成热空气以使食物脱水的空气输送单元。 风车产生提供给脱水装置的电力。 脱水装置使用绿色能源来脱水食物以保持适当的新鲜度和营养。 脱水装置易于移动,对环境友好。

    Architecture for a dual segment dual speed repeater
    4.
    发明授权
    Architecture for a dual segment dual speed repeater 有权
    双段双速中继器架构

    公开(公告)号:US06229811B1

    公开(公告)日:2001-05-08

    申请号:US09556581

    申请日:2000-04-24

    IPC分类号: H04L1228

    CPC分类号: H04L49/351 H04L49/40

    摘要: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

    摘要翻译: 本发明涉及包括耦合到所述第一和第二电路的第一电路,第二电路和逻辑电路的方法和架构。 第一段通常包括被配置为以多个速度中的一个速度操作的第一中继器核和第一端口。 第二段通常包括被配置为以多个速度中的一个速度操作的第二中继器核和第二端口。 逻辑电路可以被配置为将第一和第二端口中的每一个耦合到第一或第二中继器核心。

    Architecture for a dual segment dual speed repeater
    5.
    发明授权
    Architecture for a dual segment dual speed repeater 失效
    双段双速中继器架构

    公开(公告)号:US6055241A

    公开(公告)日:2000-04-25

    申请号:US970059

    申请日:1997-11-13

    IPC分类号: H04L12/56 H04L12/413

    CPC分类号: H04L49/351 H04L49/40

    摘要: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

    摘要翻译: 本发明涉及包括耦合到所述第一和第二电路的第一电路,第二电路和逻辑电路的方法和架构。 第一段通常包括被配置为以多个速度中的一个速度操作的第一中继器核和第一端口。 第二段通常包括被配置为以多个速度中的一个速度操作的第二中继器核和第二端口。 逻辑电路可以被配置为将第一和第二端口中的每一个耦合到第一或第二中继器核心。

    Method and apparatus for synchronizing transmitter and receiver for high
speed data communication
    6.
    发明授权
    Method and apparatus for synchronizing transmitter and receiver for high speed data communication 失效
    用于同步用于高速数据通信的发射机和接收机的方法和装置

    公开(公告)号:US5347547A

    公开(公告)日:1994-09-13

    申请号:US839978

    申请日:1992-02-21

    CPC分类号: H04J3/0608

    摘要: A method and apparatus for improving the reliability of resynchronization in a serial frame based protocol communication system which can avoid resynchronization when line loss erroneously causes data to appear as a redundant unique code pattern. The synchronization is only initiated if two such unique code pattern bytes are received within a specified time separation.

    摘要翻译: 一种用于提高基于串行帧的协议通信系统中的重新同步的可靠性的方法和装置,当线路丢失错误地导致数据出现为冗余唯一码型时,该协议通信系统可以避免重新同步。 只有在指定的时间间隔内接收到两个这样的唯一代码模式字节时才启动同步。

    Technique for generating precompensation delay for writing data to disks
    7.
    发明授权
    Technique for generating precompensation delay for writing data to disks 失效
    用于产生将数据写入磁盘的预补偿延迟的技术

    公开(公告)号:US4878028A

    公开(公告)日:1989-10-31

    申请号:US13846

    申请日:1987-02-12

    IPC分类号: G11B5/09 G11B20/10 H03K19/003

    CPC分类号: G11B20/10212 H03K19/00323

    摘要: Apparatus is disclosed for introducing a precompensation delay in the path of a data signal to be written onto a magnetic medium, such as a floppy or hard disk. The apparatus includes a current controlled oscillator made up of delay elements having current control nodes, and means for controlling the current level being drawn from the current control nodes. The latter means includes three matched voltage controlled current sources having their outputs connected through a current splitter to the current control nodes, and bypass transistors for decoupling two of the voltage controlled current sources in response to a delay selection signal indicating whether the subject data pulse should be precompensated early, nominal or late. A current mirror arrangement with a current transfer ratio adjustable through the choice of two external resistors adjusts the current outputs of two of the voltage controlled current sources, so that the current level drawn from the current control nodes is different depending on which the voltage controlled current sources is (are) selected. The apparatus also includes a master voltage controlled oscillator, located on the same chip as the above-described apparatus, with characteristics and a control voltage matched to those of the above-described apparatus. If the frequency of the master oscillator is phase locked to a multiple of the bit cell frequency, then the choice of the two external resistors adjusts the precompensation delay period as a continuous percentage of the bit cell time.

    MULTI-ELEMENT HEAT-RESISTANT ALUMINUM ALLOY MATERIAL WITH HIGH STRENGTH AND PREPARATION METHOD THEREOF
    8.
    发明申请
    MULTI-ELEMENT HEAT-RESISTANT ALUMINUM ALLOY MATERIAL WITH HIGH STRENGTH AND PREPARATION METHOD THEREOF 有权
    具有高强度的多元素耐热铝合金材料及其制备方法

    公开(公告)号:US20120152414A1

    公开(公告)日:2012-06-21

    申请号:US13392868

    申请日:2010-08-04

    IPC分类号: C22F1/057 C22C21/12

    摘要: A heat-resistant aluminum alloy material with high strength and preparation method thereof are provided. The aluminum alloy material comprises (by weight %): Cu: 1.0˜10.0, Mn: 0.05˜1.5, Cd: 0.01˜0.5, Ti: 0.01˜0.5%, B: 0.01˜0.2 or C: 0.0001˜0.15, Zr: 0.01˜1.0, R: 0.001˜3 or (R1+R2): 0.001˜3, RE: 0.05˜5, and balance Al:, wherein, R, R1, and R2 include Be, Co, Cr, Li, Mo, Nb, Ni, W. The Al alloy has the advantages of narrow quasi-solid phases temperature range of alloys, low hot cracking liability during casting improved high temperature strength and high heat resistance.

    摘要翻译: 提供了具有高强度的耐热铝合金材料及其制备方法。 铝合金材料包含(重量%):Cu:1.0〜10.0,Mn:0.05〜1.5,Cd:0.01〜0.5,Ti:0.01〜0.5%,B:0.01〜0.2或C:0.0001〜0.15,Zr: 0.01〜1.0,R:0.001〜3或(R1 + R2):0.001〜3,RE:0.05〜5,余量为Al:其中,R,R1,R2包括Be,Co,Cr,Li,Mo, Nb,Ni,W。Al合金具有合金准相固态温度范围窄,铸造时低热裂纹性能提高耐高温强度和高耐热性的优点。

    Intensive pallet
    9.
    发明申请
    Intensive pallet 审中-公开
    集约托盘

    公开(公告)号:US20100107934A1

    公开(公告)日:2010-05-06

    申请号:US12261033

    申请日:2008-10-30

    申请人: Yun Che Hsieh

    发明人: Yun Che Hsieh

    IPC分类号: B65D19/06

    摘要: An intensive pallet and a unit direction plank for the same are provided, and the pallet comprises a plurality of first direction planks spaced from each other and a plurality of second direction planks spaced from each other. The second direction plank and the first direction plank stack and cross. Two frame holes are formed in each unit of first direction plank. One frame hole communicates with a next spaced frame hole of the unit first direction plank. A plurality of first ribs are formed at the top side of each frame hole. The frame holes may be inserted by the insertion levers of a forklift. The first ribs are provided to enhance the top sides of frame holes into which the levers are inserted.

    摘要翻译: 提供了一种密集的托盘和用于其的单元方向板,并且托盘包括彼此间隔开的多个第一方向板和彼此间隔开的多个第二方向板。 第二方向木板和第一方向木板堆叠并交叉。 在第一方向板的每个单元中形成两个框架孔。 一个框架孔与单元第一方向板的下一间隔框架孔连通。 在每个框架孔的顶侧形成有多个第一肋。 框架孔可以由叉车的插入杆插入。 设置第一肋以增强插入杆的框架孔的顶侧。

    Scheme and method for testing Analog-to-Digital converters
    10.
    发明授权
    Scheme and method for testing Analog-to-Digital converters 有权
    用于测试模数转换器的方案和方法

    公开(公告)号:US07154422B2

    公开(公告)日:2006-12-26

    申请号:US11168543

    申请日:2005-06-29

    申请人: Yun-Che Wen

    发明人: Yun-Che Wen

    IPC分类号: H03M1/10

    CPC分类号: H03M1/1095 H03M1/109 H03M1/12

    摘要: The invention provides a test scheme of analog-to-digital converters and method thereof. It comprises: a control circuit, a step-ramp signal generator, a multiplexer, an n+m-bit counter, and a test analyzing circuit, wherein m=1, 2, 3 . . . , based on desired accuracy of the test scheme. A clock pulse is coupled to the n+m-bit counter and a control circuit for regulating duty cycle, amplitude, and frequency. It is also coupled to a step-ramp signal generating circuit for being integrated as a test signal source. Therefore the step-ramp signal can synchronize with the n+m-bit counter, and the output codes are applied to compare with output codes of the n-bit ADCs for completely digitally analyzing ADC's parameters. The step-ramp signal is divided into several segments, each is integrated by the regulated clock signal with different duty cycles, which increases integrating time to compensate leakage currents of the capacitor and improve linearity of the step-ramp signal.

    摘要翻译: 本发明提供了一种模拟 - 数字转换器的测试方案及其方法。 它包括:控制电路,阶梯斜坡信号发生器,多路复用器,n + m位计数器和测试分析电路,其中m = 1,2,3。 。 。 ,基于测试方案的期望精度。 时钟脉冲耦合到n + m位计数器和用于调节占空比,幅度和频率的控制电路。 它还耦合到步进斜坡信号发生电路,用于集成为测试信号源。 因此,步进斜坡信号可以与n + m位计数器同步,并且输出代码用于与n位ADC的输出代码进行比较,以完全数字分析ADC的参数。 步进斜坡信号分为几段,每个段由不同占空比的稳定时钟信号进行积分,这增加了积分时间,以补偿电容器的漏电流并提高阶梯斜坡信号的线性度。