公开(公告)号：US07606967B2

公开(公告)日：2009-10-20

申请号：US11192106

申请日：2005-07-29

申请人： Yuuji Konno

发明人： Yuuji Konno

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： H04L45/00 ,  H04L45/7453 ,  H04L49/3009 ,  H04L49/602

摘要： In a frame transfer method and apparatus, a data entry into a content addressable memory is set to enable, and upon receipt of a transfer frame addressed to a first apparatus from a line bus, header information of the frame is entered into the content addressable memory based on the setting that the entry is enabled. The frame prepared based on header information entered into a content addressable memory of a second apparatus and transmitted by the second apparatus can be used, and the frame is discarded when it is not addressed to the first apparatus. Furthermore, normal frame processing is performed when the entry is not enabled by the setting.

摘要翻译： 在帧传送方法和装置中，设置到内容可寻址存储器中的数据输入，使得能够在从线路总线接收到寻址到第一装置的传送帧时，将帧的标题信息输入到内容可寻址存储器 基于条目启用的设置。 可以使用基于输入到第二装置的内容可寻址存储器并由第二装置发送的标题信息准备的帧，并且当帧未被寻址到第一装置时丢弃该帧。 此外，当条目未被该设置启用时，执行正常的帧处理。

公开(公告)号：US08769142B2

公开(公告)日：2014-07-01

申请号：US12824458

申请日：2010-06-28

申请人： Yuuji Konno ,  Hiroyuki Wada ,  Hiromi Fukumura ,  Hiroshi Murakami

发明人： Yuuji Konno ,  Hiroyuki Wada ,  Hiromi Fukumura ,  Hiroshi Murakami

IPC分类号： G06F15/16

CPC分类号： H04L12/6418

摘要： A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.

摘要翻译： 一种设置具有多个处理装置的信息处理装置的传送速率的方法，所述处理装置包括处理器，其输出数据并由一个或多个数据传送装置连接，用于传送从处理器输出的数据，所述方法包括获得指示 将所述信息处理装置划分为包括所述多个处理装置中的至少一个处理装置的多个分区的方式，并且将各广播数据的分区的传送速率设定为在各分区的多个处理装置中包含的所有处理器 对获得的划分信息。

公开(公告)号：US08164973B2

公开(公告)日：2012-04-24

申请号：US12780004

申请日：2010-05-14

申请人： Yuuji Konno ,  Hiroshi Murakami

发明人： Yuuji Konno ,  Hiroshi Murakami

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C8/04 ,  G11C8/18 ,  G11C19/00 ,  G11C19/28

摘要： A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.

摘要翻译： 存储装置包括：多个存储部分，每个存储部分对应于多个地址中的每一个; 读指针寄存器，其输出指示从其读取数据的存储部分的地址的读指针; 写指针寄存器，其输出指示写入数据的存储部的地址的写指针; 接收与第一频率不同的第二频率的第一频率和第二时钟信号的第一时钟信号的控制电路基于读取的指针确定指示第一时钟信号或第二时钟信号的选择信号，或者 所述写入指针用于所述多个存储部分中的每一个，并输出所述选择信号; 并且选择电路选择由选择信号指示的信号，并输出所选择的信号。

公开(公告)号：US20110004740A1

公开(公告)日：2011-01-06

申请号：US12824458

申请日：2010-06-28

申请人： Yuuji KONNO ,  Hiroyuki Wada ,  Hiromi Fukumura ,  Hiroshi Murakami

发明人： Yuuji KONNO ,  Hiroyuki Wada ,  Hiromi Fukumura ,  Hiroshi Murakami

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： H04L12/6418

摘要： A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.

摘要翻译： 一种设置具有多个处理装置的信息处理装置的传送速率的方法，所述处理装置包括处理器，其输出数据并由一个或多个数据传送装置连接，用于传送从处理器输出的数据，所述方法包括获得指示 将所述信息处理装置划分为包括所述多个处理装置中的至少一个处理装置的多个分区的方式，并且将各广播数据的分区的传送速率设定为在各分区的多个处理装置中包含的所有处理器 对获得的划分信息。

公开(公告)号：US20060212598A1

公开(公告)日：2006-09-21

申请号：US11192106

申请日：2005-07-29

申请人： Yuuji Konno

发明人： Yuuji Konno

IPC分类号： G06F15/16 ,  G06F12/00

CPC分类号： H04L45/00 ,  H04L45/7453 ,  H04L49/3009 ,  H04L49/602

摘要： In a frame transfer method and apparatus, a data entry into a content addressable memory is set to enable, and upon receipt of a transfer frame addressed to a first apparatus from a line bus, header information of the frame is entered into the content addressable memory based on the setting that the entry is enabled. The frame prepared based on header information entered into a content addressable memory of a second apparatus and transmitted by the second apparatus can be used, and the frame is discarded when it is not addressed to the first apparatus. Furthermore, normal frame processing is performed when the entry is not enabled by the setting.

公开(公告)号：US20060085694A1

公开(公告)日：2006-04-20

申请号：US11018986

申请日：2004-12-21

申请人： Yuuji Konno

发明人： Yuuji Konno

IPC分类号： G06F11/00

CPC分类号： H04L43/50

摘要： In a communication apparatus performing communication using IP packets, a diagnostic frame terminator terminates a series of latest status information of diagnosed devices recorded in a diagnostic frame every time the diagnostic frame sequentially passes through a series of diagnosed devices connected in cascade; a content addressable memory preliminarily stores therein as a single entry a series of normal status information in which each status information of the series of diagnosed devices in a normal state is arranged in an order of connection of the diagnosed devices, and generates an abnormality notification when the terminated series of latest status information does not hit the entry; a status information storage stores the terminated series of latest status information; and a CPU acquires, upon receipt of the abnormality notification, the terminated series of the latest status information from the status information storage to be outputted.

摘要翻译： 在使用IP分组进行通信的通信装置中，每当诊断帧依次通过串联连接的一系列诊断装置时，诊断帧终止符终止记录在诊断帧中的诊断装置的一系列最新状态信息; 内容可寻址存储器在其中预先存储一系列正常状态信息的一系列正常状态信息，其中正常状态下的一系列诊断装置的每个状态信息按照诊断装置的连接顺序排列，并且当 终止的系列最新状态信息不会打入条目; 状态信息存储存储终止的一系列最新状态信息; 并且CPU从接收到异常通知时，从要输出的状态信息存储器中获取终止的一系列最新状态信息。

公开(公告)号：US20100223488A1

公开(公告)日：2010-09-02

申请号：US12780004

申请日：2010-05-14

申请人： Yuuji Konno ,  Hiroshi Murakami

发明人： Yuuji Konno ,  Hiroshi Murakami

IPC分类号： G06F12/00 ,  G06F1/06

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C8/04 ,  G11C8/18 ,  G11C19/00 ,  G11C19/28

摘要： A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.

摘要翻译： 存储装置包括：多个存储部分，每个存储部分对应于多个地址中的每一个; 读指针寄存器，其输出指示从其读取数据的存储部分的地址的读指针; 写指针寄存器，其输出指示写入数据的存储部的地址的写指针; 接收与第一频率不同的第二频率的第一频率和第二时钟信号的第一时钟信号的控制电路基于读取的指针确定指示第一时钟信号或第二时钟信号的选择信号，或者 所述写入指针用于所述多个存储部分中的每一个，并输出所述选择信号; 并且选择电路选择由选择信号指示的信号，并输出所选择的信号。

公开(公告)号：US07290173B2

公开(公告)日：2007-10-30

申请号：US11018986

申请日：2004-12-21

申请人： Yuuji Konno

发明人： Yuuji Konno

IPC分类号： G06F11/00

CPC分类号： H04L43/50

摘要： In a communication apparatus performing communication using IP packets, a diagnostic frame terminator terminates a series of latest status information of diagnosed devices recorded in a diagnostic frame every time the diagnostic frame sequentially passes through a series of diagnosed devices connected in cascade; a content addressable memory preliminarily stores therein as a single entry a series of normal status information in which each status information of the series of diagnosed devices in a normal state is arranged in an order of connection of the diagnosed devices, and generates an abnormality notification when the terminated series of latest status information does not hit the entry; a status information storage stores the terminated series of latest status information; and a CPU acquires, upon receipt of the abnormality notification, the terminated series of the latest status information from the status information storage to be outputted.

摘要翻译： 在使用IP分组进行通信的通信装置中，每当诊断帧依次通过串联连接的一系列诊断装置时，诊断帧终止符终止记录在诊断帧中的诊断装置的一系列最新状态信息; 内容可寻址存储器在其中预先存储一系列正常状态信息的一系列正常状态信息，其中正常状态下的一系列诊断装置的每个状态信息按照诊断装置的连接顺序排列，并且当 终止的系列最新状态信息不会打入条目; 状态信息存储存储终止的一系列最新状态信息; 并且CPU从接收到异常通知时，从要输出的状态信息存储器中获取终止的一系列最新状态信息。

公开(公告)号：US06899567B2

公开(公告)日：2005-05-31

申请号：US10625336

申请日：2003-07-22

申请人： Yuuji Konno

发明人： Yuuji Konno

IPC分类号： G06F1/18 ,  G11C5/00 ,  G11C5/04 ,  H05K1/14 ,  H05K7/14 ,  H01R24/00

CPC分类号： G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  G11C5/04 ,  H05K1/141 ,  H05K2201/10189 ,  H05K2201/10522

摘要： A memory socket, particularly a detachable memory card (DIMM), in which equal-length wiring can be obtained in a wiring design, is provided. A memory socket for mounting a detachable memory card on a circuit board is comprised of a first memory socket in which a first memory card is inserted, with a surface facing upward and a second memory socket in which a second memory card is inserted, with the other surface facing upward. The first memory socket and the second memory socket are arranged adjacent each other on said circuit board. The first and second memory cards are inserted from the outside of the first and second memory sockets, in opposite directions.

摘要翻译： 提供了一种存储器插座，特别是可拆卸存储卡（DIMM），其中可以在布线设计中获得等长布线。 用于将可拆卸存储卡安装在电路板上的存储器插座包括第一存储器插槽，其中第一存储卡被插入，其中表面朝上，第二存储器插槽插入第二存储卡，第二存储器插槽中插入有第二存储卡， 其他表面朝上。 第一存储器插座和第二存储器插槽在所述电路板上彼此相邻布置。 第一和第二存储卡从第一和第二存储器插槽的外部以相反方向插入。