公开(公告)号：US20190095330A1

公开(公告)日：2019-03-28

申请号：US15718564

申请日：2017-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. ROBERTS ,  Elliot H. MEDNICK

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/084 ,  G06F12/0804

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/507 ,  G06F2212/60 ,  G06F2212/621

Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.

公开(公告)号：US20190129489A1

公开(公告)日：2019-05-02

申请号：US15795719

申请日：2017-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Elliot H. MEDNICK ,  Edward MCLELLAN

IPC: G06F1/32 ,  G06F12/0875 ,  G06F12/084 ,  G06F3/06

Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.