公开(公告)号：US20190129651A1

公开(公告)日：2019-05-02

申请号：US15794457

申请日：2017-10-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John WUU ,  Michael K. CIRAULA ,  Russell SCHREIBER ,  Samuel NAFFZIGER

IPC: G06F3/06 ,  G06F12/1009

Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

公开(公告)号：US20210067161A1

公开(公告)日：2021-03-04

申请号：US16817976

申请日：2020-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Russell SCHREIBER

IPC: H03K19/00 ,  H03K19/0175 ,  H04L25/20

Abstract: An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.