公开(公告)号：US11210757B2

公开(公告)日：2021-12-28

申请号：US16713472

申请日：2019-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Todd Martin ,  Tad Litwiller ,  Nishank Pathak ,  Mangesh P. Nijasure

IPC: G06T1/20 ,  H04L12/863 ,  H04L12/861

Abstract: A graphics processing unit (GPU) includes a packet management component that automatically aggregates data from input packets. In response to determining that a received first input packet does not indicate a send condition, and in response to determining that a generated output packet would be smaller than an output size threshold, the packet management component aggregates data corresponding to the first input packet with data corresponding to a second input packet stored at a packet buffer. In response to determining that a received third input packet indicates a send condition, the packet management component sends the aggregated data to a compute unit in an output packet and performs an operation indicated by the send condition.

公开(公告)号：US11776085B2

公开(公告)日：2023-10-03

申请号：US17123978

申请日：2020-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nishank Pathak ,  Randy Wayne Ramsey ,  Tad Litwiller ,  Rex Eldon McCrary

IPC: G06T1/20 ,  G06F1/08 ,  G06T17/10 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F1/08 ,  G06T15/005 ,  G06T17/10

Abstract: A processing system includes a graphics pipeline that executes a first shader of a first type and a second shader of a second type. In some cases, the first shader is a geometry shader and the second shader is a pixel shader. The processing system also includes buffers that hold primitives generated by the first shader and provide the primitives to the second shader. The processing system also includes a primitive hub that monitors fullness of the buffers. Launching of waves from the first shader is throttled based on the fullness of the buffers. A shader processor input (SPI) selectively throttles the waves launched by the geometry shader based on a signal from the primitive hub indicating the fullness, an indication of relative resource usage of geometry waves and pixel waves in the graphics pipeline, or an indication of lifetimes of the geometry waves.

公开(公告)号：US11532066B2

公开(公告)日：2022-12-20

申请号：US17318523

申请日：2021-05-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mangesh P. Nijasure ,  Tad Litwiller ,  Todd Martin ,  Nishank Pathak

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/38

Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.

公开(公告)号：US11010862B1

公开(公告)日：2021-05-18

申请号：US16683868

申请日：2019-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mangesh P. Nijasure ,  Tad Litwiller ,  Todd Martin ,  Nishank Pathak

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/48 ,  G06T15/00

Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.