公开(公告)号：US11586563B2

公开(公告)日：2023-02-21

申请号：US17130604

申请日：2020-12-22

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Max Ruttenberg ,  Vendula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Anthony Gutierrez ,  Mark H. Oskin

IPC分类号： G06F13/16 ,  G11C11/4076

摘要： A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

公开(公告)号：US12079145B2

公开(公告)日：2024-09-03

申请号：US18103240

申请日：2023-01-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Max Ruttenberg ,  Vendula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Anthony Gutierrez ,  Mark H. Oskin

IPC分类号： G06F13/16 ,  G11C11/4076

CPC分类号： G06F13/1668 ,  G11C11/4076

摘要： A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.