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公开(公告)号：US20230094508A1
公开(公告)日：2023-03-30
申请号：US17491304
申请日：2021-09-30
发明人： Salonik Resch , Anthony Gutierrez , Yasuko Eckert , Vedula Venkata Srikant Bharadwaj , Mark H. Oskin
摘要： An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.
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公开(公告)号：US11550627B2
公开(公告)日：2023-01-10
申请号：US17215171
申请日：2021-03-29
发明人： Anthony Gutierrez , Sooraj Puthoor
摘要： A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
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公开(公告)号：US11086809B2
公开(公告)日：2021-08-10
申请号：US16693638
申请日：2019-11-25
发明人： Anthony Gutierrez
IPC分类号： G06F13/36 , G06F13/362 , G06F11/34 , G06F11/30
摘要： Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.
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公开(公告)号：US20230153672A1
公开(公告)日：2023-05-18
申请号：US17840417
申请日：2022-06-14
发明人： Salonik Resch , Anthony Gutierrez , Mark H. Oskin
IPC分类号： G06N10/20
CPC分类号： G06N10/20
摘要： An electronic device includes a quantum processor including a plurality of qubits. The quantum processor runs a plurality of instances of a quantum program using a separate set of qubits from among the qubits for each instance of the quantum program. The quantum processor then sets quantum states for ancilla qubits from among the qubits based on quantum states of respective groups of associated qubits from the separate sets of qubits. The quantum processor next provides an output of the instances of the quantum program based on the quantum states of the ancilla qubits.
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公开(公告)号：US11586563B2
公开(公告)日：2023-02-21
申请号：US17130604
申请日：2020-12-22
发明人： Max Ruttenberg , Vendula Venkata Srikant Bharadwaj , Yasuko Eckert , Anthony Gutierrez , Mark H. Oskin
IPC分类号： G06F13/16 , G11C11/4076
摘要： A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.
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公开(公告)号：US10963299B2
公开(公告)日：2021-03-30
申请号：US16134695
申请日：2018-09-18
发明人： Anthony Gutierrez , Sooraj Puthoor
摘要： A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
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公开(公告)号：US11989591B2
公开(公告)日：2024-05-21
申请号：US17037727
申请日：2020-09-30
IPC分类号： G06F9/50 , G06F9/30 , G06F9/38 , G06F9/4401
CPC分类号： G06F9/505 , G06F9/30043 , G06F9/3802 , G06F9/3836 , G06F9/4403 , G06F9/4418
摘要： A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.
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公开(公告)号：US11797410B2
公开(公告)日：2023-10-24
申请号：US17526218
申请日：2021-11-15
发明人： Shrikanth Ganapathy , Yasuko Eckert , Anthony Gutierrez , Karthik Ramu Sangaiah , Vedula Venkata Srikant Bharadwaj
CPC分类号： G06F11/3051 , G06F11/3024 , G06F15/80 , G06F11/3409 , Y02D10/00
摘要： A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.
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公开(公告)号：US20230097115A1
公开(公告)日：2023-03-30
申请号：US17485662
申请日：2021-09-27
发明人： Anthony Gutierrez , Sooraj Puthoor
摘要： A processing system executes a specialized wavefront, referred to as a “garbage collecting wavefront” or GCWF, to identify and deallocate resources such as, for example, scalar registers, vector registers, and local data share space, that are no longer being used by wavefronts of a workgroup executing at the processing system (i.e., dead resources). In some embodiments, the GCWF is programmed to have compiler information regarding the resource requirements of the other wavefronts of the workgroup and specifies the program counter after which there will be a permanent drop in resource requirements for the other wavefronts. In other embodiments, the standard compute wavefronts signal the GCWF when they have completed using resources. The GCWF sends a command to deallocate the dead resources so the dead resources can be made available for additional wavefronts.
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公开(公告)号：US20220188208A1
公开(公告)日：2022-06-16
申请号：US17118404
申请日：2020-12-10
IPC分类号： G06F11/30 , G06F1/20 , G06F12/0815 , G11C11/406 , G06F9/48 , G06F9/30
摘要： A method may include, in response to a change in an operating parameter of a processing unit, modifying a signal pathway to a processing circuit component of the processing unit, and communicating with the processing circuit component via the signal pathway.
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