公开(公告)号：US09374080B2

公开(公告)日：2016-06-21

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。

公开(公告)号：US08570090B2

公开(公告)日：2013-10-29

申请号：US13774690

申请日：2013-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： William B. Gist, III ,  Warren Anderson

IPC: H03K5/08

CPC classification number: H01L27/0285

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering. This also lengthens the time that the clamp circuit remains in the ESD-triggered state during human body model (HBM) or other long duration detected ESD events.

公开(公告)号：US20150130519A1

公开(公告)日：2015-05-14

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K3/01

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。

公开(公告)号：US20130163131A1

公开(公告)日：2013-06-27

申请号：US13774690

申请日：2013-02-22

Applicant: Advanced Micro Devices, Inc.

Inventor： William B. Gist, III ,  Warren Anderson

IPC: H02H9/04

CPC classification number: H01L27/0285

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering. This also lengthens the time that the clamp circuit remains in the ESD-triggered state during human body model (HBM) or other long duration detected ESD events.

Abstract translation: 描述了包括多个p型沟道金属氧化物半导体（PMOS）和n型沟道金属氧化物半导体（NMOS）晶体管的电子元件保护电源钳位电路。 这些钳位电路使用反馈锁存电路来保持静电放电（ESD）触发状态，并有效地传导已经转移到电源中的ESD电流，以便耗散ESD能量。 如果钳位电路未触发上电，则反馈闭锁电路还将钳位晶体管保持在其截止状态，从而在正常操作期间增强钳位电路对噪声的抗扰性。 关键节点的无源电阻初始化为非触发状态，以及大型ESD钳位晶体管的无源电阻栅极输入负载，进一步增强了钳位电路对错误触发的抗扰度。 这也延长了在人体模型（HBM）或其他长时间检测到的ESD事件期间钳位电路保持在ESD触发状态的时间。