公开(公告)号：US20150130519A1

公开(公告)日：2015-05-14

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K3/01

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。

公开(公告)号：US09274938B2

公开(公告)日：2016-03-01

申请号：US13737306

申请日：2013-01-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Shawn Searles ,  Nicholas Todd Humphries ,  Brian W. Amick ,  Richard W. Reeves ,  Hanwoo Cho ,  Ronald L. Pettyjohn

IPC: G06F12/00 ,  G06F1/32 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/00 ,  G06F1/3275 ,  G06F13/1689 ,  G06F13/4072 ,  G06F13/4086 ,  Y02D10/14

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

公开(公告)号：US09374080B2

公开(公告)日：2016-06-21

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。