公开(公告)号：US12118411B2

公开(公告)日：2024-10-15

申请号：US16568038

申请日：2019-09-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sneha V. Desai ,  Michael Estlick ,  Erik Swanson ,  Anilkumar Ranganagoudra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/52

CPC classification number: G06F9/544 ,  G06F9/505 ,  G06F9/5083 ,  G06F9/528 ,  G06F9/546

Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.