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    Distributed scheduler providing execution pipe balance
    1.
    发明授权
    Distributed scheduler providing execution pipe balance 有权

    公开(公告)号：US12118411B2

    公开(公告)日：2024-10-15

    申请号：US16568038

    申请日：2019-09-11

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Sneha V. Desai ,  Michael Estlick ,  Erik Swanson ,  Anilkumar Ranganagoudra

    IPC: G06F9/54 ,  G06F9/50 ,  G06F9/52

    CPC classification number: G06F9/544 ,  G06F9/505 ,  G06F9/5083 ,  G06F9/528 ,  G06F9/546

    Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.

    Register renaming after a non-pickable scheduler queue
    2.
    发明授权
    Register renaming after a non-pickable scheduler queue 有权

    公开(公告)号：US11281466B2

    公开(公告)日：2022-03-22

    申请号：US16660495

    申请日：2019-10-22

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Arun A. Nair ,  Michael Estlick ,  Erik Swanson ,  Sneha V. Desai ,  Donglin Ji

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.

    Register based SIMD lookup table operations
    3.
    发明授权
    Register based SIMD lookup table operations 有权

    公开(公告)号：US12299445B2

    公开(公告)日：2025-05-13

    申请号：US17833504

    申请日：2022-06-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Yasuko Eckert ,  Bradford Beckmann ,  Michael Estlick ,  Jay Fleischman

    IPC: G06F9/30

    Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.

    Multi-modal gather operation
    7.
    发明授权
    Multi-modal gather operation 有权

    公开(公告)号：US11842200B2

    公开(公告)日：2023-12-12

    申请号：US16586247

    申请日：2019-09-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John M. King ,  Magiting Talisayon ,  Michael Estlick

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3887 ,  G06F9/3013 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3861

    Abstract: An apparatus includes a plurality of load buses and a load store unit that includes a plurality of load ports to access the plurality of load buses. The load store unit performs a gather operation to concurrently gather a plurality of subsets of data from a memory via the plurality of load buses in a first mode. The apparatus also includes a register that is partitioned into a plurality of portions to hold the plurality of subsets of data provided by the load store unit. The load store unit ignores exceptions or faults while performing the gather operation in the first mode and transitions to a second mode in response to an exception or fault. Two lanes are dispatched to concurrently perform the gather operation per clock cycle in the first mode and a single lane is dispatched to perform the gather operation per clock cycle in the second mode.

    ACCELERATED REVERSAL OF SPECULATIVE STATE CHANGES AND RESOURCE RECOVERY
    8.
    发明申请
    ACCELERATED REVERSAL OF SPECULATIVE STATE CHANGES AND RESOURCE RECOVERY 有权
    调整状态变化和资源恢复的加速反转

    公开(公告)号：US20140372732A1

    公开(公告)日：2014-12-18

    申请号：US13918863

    申请日：2013-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jay Fleischman ,  Michael Estlick

    IPC: G06F9/38

    CPC classification number: G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861

    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.

    Abstract translation: 一种方法包括以反向程序顺序来撤销由先前在处理设备中执行的推测性指令引起的处理设备的状态的改变，并且响应于由于指令的发送中断而先前分配给推测指令的资源 冲突的投机指示。 处理器设备包括用于存储等待退休的指令的条目的退出队列和有限状态机。 有限状态机是响应于先前调度以在处理设备中执行的推测性指令的刷新来中断指令的分派，并且以反向程序顺序撤销由推测指令引起的处理设备的状态的改变，同时 释放以前分配给投机指示的资源。

    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION
    9.
    发明公开
    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION 审中-公开

    公开(公告)号：US20240319964A1

    公开(公告)日：2024-09-26

    申请号：US18126107

    申请日：2023-03-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Lee Evan Eisen ,  Michael Estlick ,  Jay Fleischman ,  Matthew R. Poremba ,  Gabriel H. Loh

    IPC: G06F7/503

    CPC classification number: G06F7/503

    Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
    10.
    发明公开
    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION 审中-公开

    公开(公告)号：US20240111489A1

    公开(公告)日：2024-04-04

    申请号：US17955634

    申请日：2022-09-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Michael Estlick ,  Masab Ahmad ,  Gabriel H. Loh

    IPC: G06F7/498 ,  G06F7/506

    CPC classification number: G06F7/4981 ,  G06F7/506

    Abstract: A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

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