公开(公告)号：US20210056042A1

公开(公告)日：2021-02-25

申请号：US16548692

申请日：2019-08-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sonu ARORA ,  Paul BLINZER ,  Philip NG ,  Nippon Harshadk RAVAL

IPC: G06F12/1027 ,  G06F13/16

Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

公开(公告)号：US20210191879A1

公开(公告)日：2021-06-24

申请号：US16723185

申请日：2019-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sonu ARORA ,  Benjamin TSIEN ,  Alexander J. BRANOVER

IPC: G06F12/14 ,  G06F12/06 ,  G06F12/0877 ,  G06F9/54 ,  G06F9/30 ,  G06F9/50 ,  G06F11/30 ,  G06F12/1009 ,  G06F12/1027

Abstract: A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.