公开(公告)号：US20120088371A1

公开(公告)日：2012-04-12

申请号：US13089374

申请日：2011-04-19

Applicant: ALOK RANJAN ,  NICOLAS GANI ,  MEIHUA SHEN ,  ANISUL H. KHAN

Inventor： ALOK RANJAN ,  NICOLAS GANI ,  MEIHUA SHEN ,  ANISUL H. KHAN

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/32697 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/32136

Abstract: Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.

Abstract translation: 本文提供了使用脉冲DC电压蚀刻基板的方法。 在一些实施例中，用于蚀刻设置在处理室内的衬底支撑件上的衬底的方法的方法可包括向处理室提供工艺气体; 从工艺气体形成等离子体; 向设置在处理室内的第一电极施加脉冲DC电压; 并在施加脉冲DC电压的同时刻蚀衬底。

公开(公告)号：US20090017633A1

公开(公告)日：2009-01-15

申请号：US11777259

申请日：2007-07-12

Applicant: NICOLAS GANI ,  Meihua Shen ,  Shashank Deshmukh

Inventor： NICOLAS GANI ,  Meihua Shen ,  Shashank Deshmukh

IPC: H01L21/302

CPC classification number: H01L21/32137 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/823828 ,  H01L29/517

Abstract: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.

Abstract translation: 本文提供了用于制造CMOS逻辑门的蚀刻方法。 在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及 形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。