Inter-integrated circuit (I2C) apparatus

    公开(公告)号:US11829319B2

    公开(公告)日:2023-11-28

    申请号:US17613298

    申请日:2020-05-28

    CPC classification number: G06F13/4291 G06F13/4022 G06F13/4072

    Abstract: An I2C apparatus (100) comprising: a master device (102) and two slave devices connected through an I2C bus, whereby the two slave devices are programmed with the same default device address. A first slave device (108) is connected to the bus in a conventional configuration whereas a second slave device (110) is connected to the bus in a cross connected configuration such that a clock pin of the second slave is connected to the serial data line and the data pin of the second slave is connected to the serial clock line. In response to a detection that the data pin of the second slave is connected to the serial clock line, the second slave swaps the lines going from the clock and data pins to processing logic of the second slave; and modifies its default device address to ensure that each slave device has a unique device address.

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