公开(公告)号：US20240063345A1

公开(公告)日：2024-02-22

申请号：US18260621

申请日：2021-01-19

Applicant: ams-OSRAM International GmbH

Inventor： Fabian KOPP ,  Attila MOLNAR ,  Hong Pin LOH ,  Ban Loong Chris NG

IPC: H01L33/46 ,  H01L25/075

CPC classification number: H01L33/46 ,  H01L25/0753 ,  H01L2933/0025

Abstract: A radiation-emitting semiconductor chip may include a semiconductor layer sequence having a first semiconductor layer of a first doping type and a second semiconductor layer of a second doping type. The chip may also include a first dielectric layer and a second dielectric layer arranged on the semiconductor layer sequence. A first recess may be arranged in the semiconductor layer sequence in a border region of the radiation-emitting semiconductor chip completely penetrating the first semiconductor layer. The first dielectric layer may cover the semiconductor layer sequence in the border region completely. The border region may be free of the second dielectric layer in an edge region. In addition, a method is disclosed for producing a radiation-emitting semiconductor chip.

公开(公告)号：US20250087613A1

公开(公告)日：2025-03-13

申请号：US18723879

申请日：2021-12-27

Applicant: ams-OSRAM International GmbH

Inventor： Fabian KOPP ,  Attila MOLNAR ,  Ban Loong Chris NG ,  Hein Yoong LEOW

IPC: H01L23/00

Abstract: A semiconductor chip includes an epitaxial semiconductor layer sequence, a solder layer arranged over a back side face of the epitaxial semiconductor layer sequence, a buffer layer arranged between the back side face of the epitaxial semiconductor layer sequence and the solder layer. The buffer layer includes a porous and/or rough metal.

公开(公告)号：US20230084844A1

公开(公告)日：2023-03-16

申请号：US17799295

申请日：2021-02-17

Applicant: AMS-OSRAM International GmbH

Inventor： Fabian KOPP ,  Attila MOLNAR ,  Lutz HOEPPEL

IPC: H01L33/60

Abstract: An optoelectronic semiconductor device may include a carrier comprising a patterned surface and a semiconductor layer sequence arranged on the carrier. The semiconductor layer sequence may include a first semiconductor layer having a first surface, a second semiconductor layer having a first surface, and a first main surface and a second main surface opposite the first main surface. The first surfaces of the first and second semiconductor layers may be at least partly arranged at the first main surface. The second main surface may face the patterned surface of the carrier, and at least one side face may connect the first and second main surfaces. The device may further include a directionally reflective layer and a planarization layer. The planarization layer may be arranged between the patterned surface and the directionally reflective layer. Moreover, a method for producing an optoelectronic semiconductor device is also disclosed.