Techniques for generating multiple low noise reference voltages

    公开(公告)号:US10673415B2

    公开(公告)日:2020-06-02

    申请号:US16048860

    申请日:2018-07-30

    Abstract: Techniques to generate two separate temperature independent reference voltages. The reference voltages can be generated using a chain of ΔVBE cells. A cross-quad ΔVBE-cell-based bandgap voltage reference can cancel out noise of associated current sources by forcing them to correlate. Several ΔVBE stages can be cascaded together to generate an appreciable PTAT component that can cancel the CTAT component from VBE. In some example configurations, only BJTs are used—without requiring use of an amplifier—to generate the bandgap voltages; in this way, extremely low noise voltage references can be generated. The PTAT and the CTAT voltages can be combined to generate a bandgap voltage of approximately VG0 or approximately 2VG0.

    TECHNIQUES FOR GENERATING MULTIPLE LOW NOISE REFERENCE VOLTAGES

    公开(公告)号:US20200036366A1

    公开(公告)日:2020-01-30

    申请号:US16048860

    申请日:2018-07-30

    Abstract: Techniques to generate two separate temperature independent reference voltages. The reference voltages can be generated using a chain of ΔVBE cells. A cross-quad ΔVBE-cell-based bandgap voltage reference can cancel out noise of associated current sources by forcing them to correlate. Several ΔVBE stages can be cascaded together to generate an appreciable PTAT component that can cancel the CTAT component from VBE. In some example configurations, only BJTs are used—without requiring use of an amplifier—to generate the bandgap voltages; in this way, extremely low noise voltage references can be generated. The PTAT and the CTAT voltages can be combined to generate a bandgap voltage of approximately VG0 or approximately 2VG0.

    Low noise precision input stage for analog-to-digital converters
    5.
    发明授权
    Low noise precision input stage for analog-to-digital converters 有权
    模数转换器的低噪声精度输入级

    公开(公告)号:US09391628B1

    公开(公告)日:2016-07-12

    申请号:US14967880

    申请日:2015-12-14

    CPC classification number: H03M1/1245 G11C27/026

    Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

    Abstract translation: 模数转换器(ADC)的输入级包括至少一个用于采集相位中的输入信号的采样电容器(SC),用于向SC提供输入信号的电容增益放大器(CGA)以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽,并且在所述获取阶段的后续,第二部分期间具有第二带宽,第二带宽小于第一带宽。 以这种方式,首先,以更高的第一带宽对输入信号进行采样,从而可利用使用高带宽CGA来最小化SC上的稳定误差,并且接下来在相同获取阶段的第二部分期间 ,输入信号以较低,第二带宽进行采样,有利于降低使用高带宽CGA导致的噪声。

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