公开(公告)号：US10020068B2

公开(公告)日：2018-07-10

申请号：US15266741

申请日：2016-09-15

Applicant: Analog Devices Global

Inventor： Christopher Peter Hurrell ,  Rares Andrei Bodnar ,  Pasquale Delizia

IPC: G11C27/02 ,  H03K17/693

CPC classification number: G11C27/02 ,  G11C7/02 ,  G11C27/024 ,  H03K17/693

Abstract: Distortion in a combined sample and hold circuit and multiplexer can be reduced by dividing the sample and hold circuit and the multiplexer up into main and compensation signal channels, and considering the total error signal that arises during an acquire phase across both the switches of the multiplexer and the input switches of the sample and hold stage as a single error signal that has to be compensated. This compensation is then achieved by causing the same error voltages to be induced in both the main and compensation channels of the whole MUX and sample and hold circuit, such that errors can be made to cancel, thus improving the performance of the stage.

公开(公告)号：US09800262B1

公开(公告)日：2017-10-24

申请号：US15258910

申请日：2016-09-07

Applicant: Analog Devices Global

Inventor： Roberto Sergio Matteo Maurino ,  Sanjay Rajasekhar ,  Pasquale Delizia ,  Colin G. Lyden ,  Gabriel Banarie

IPC: H03M3/00 ,  H03M1/08

CPC classification number: H03M3/464 ,  H03M1/08 ,  H03M3/34 ,  H03M3/452

Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

公开(公告)号：US09391628B1

公开(公告)日：2016-07-12

申请号：US14967880

申请日：2015-12-14

Applicant: ANALOG DEVICES GLOBAL

Inventor： Colin G. Lyden ,  Pasquale Delizia ,  Sanjay Rajasekhar ,  Yogesh Jayarman Sharma ,  Arthur J. Kalb ,  Marvin L. Shu ,  Gerard Mora-Puchalt ,  Roberto S. Maurino

IPC: H03M1/38 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/1245 ,  G11C27/026

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

Abstract translation: 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。