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公开(公告)号：US20230229902A1
公开(公告)日：2023-07-20
申请号：US17579477
申请日：2022-01-19
Applicant: Apple Inc.
Inventor： Christopher L. Mills
CPC classification number: G06N3/0635 , G06F7/06
Abstract: Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a parallel sorting operation on input data. The neural engine circuit includes operation circuits and an accumulator circuit coupled to the outputs of the operation circuits. Each of the operation circuits operates in parallel and is configured to compare a field of a first record of a first set of records and a corresponding field of a second record of a second set of records to generate a comparison result on values in the field and the corresponding field. The accumulator circuit includes a record store storing records that are involved in the parallel sorting operation and a sideband register that stores the comparison results generated by the operation circuits.
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公开(公告)号：US11487846B2
公开(公告)日：2022-11-01
申请号：US15971444
申请日：2018-05-04
Applicant: Apple Inc.
Inventor： Christopher L. Mills , Erik K. Norden , Sung Hee Park
IPC: G06F17/16
Abstract: Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.
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公开(公告)号：US20220019875A1
公开(公告)日：2022-01-20
申请号：US17473454
申请日：2021-09-13
Applicant: Apple Inc.
Inventor： Liran Fishel , Sung Hee Park , Christopher L. Mills
IPC: G06N3/04
Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.
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公开(公告)号：US20190340502A1
公开(公告)日：2019-11-07
申请号：US15971635
申请日：2018-05-04
Applicant: Apple Inc.
Inventor： Sung Hee Park , Seungjin Lee , Christopher L. Mills
Abstract: Embodiments relate to a neural processor circuit including neural engines, a buffer, and a kernel access circuit. The neural engines perform convolution operations on input data and kernel data to generate output data. The buffer is between the neural engines and a memory external to the neural processor circuit. The buffer stores input data for sending to the neural engines and output data received from the neural engines. The kernel access circuit receives one or more kernels from the memory external to the neural processor circuit. The neural processor circuit operates in one of multiple modes, at least one of which divides a convolution operation into multiple independent convolution operations for execution by the neural engines.
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5.发明申请公开(公告)号：US20190340498A1
公开(公告)日：2019-11-07
申请号：US15971786
申请日：2018-05-04
Applicant: Apple Inc.
Inventor： Christopher L. Mills
Abstract: Embodiments relate to a neural processor circuit that includes multiple neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits receives multiple sub-channels of a portion of input data from the data buffer. Neural engine circuit further receives a kernel of the one or more kernels from the kernel fetcher circuit, wherein the kernel was decomposed into a corresponding sub-kernel for each sub-channel of the portion of the input data. Neural engine circuit performs a convolution operation on each sub-channel of the portion of the input data and the corresponding sub-kernel. Neural engine circuit accumulates corresponding outputs of each sub-channel portion of the convolution operation to generate a single channel of the output data.
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Patent Agency Ranking
公开(公告)号：US09210391B1
公开(公告)日：2015-12-08
申请号：US14449019
申请日：2014-07-31
Applicant: Apple Inc.
Inventor： Christopher L. Mills
CPC classification number: G06T3/4015 , H04N9/045 , H04N9/07 , H04N9/64
Abstract: An input rescale module for an image signal processor (ISP) that downscales sensor data in the horizontal and vertical dimensions. The module may demosaic the sensor data to generate RGB data. Horizontal filtering may be applied to horizontally downsize the RGB data. The RGB data is converted to YCC, chroma 4:4:4. The chroma 4:4:4 is then horizontally filtered to generate chroma 4:2:2. Dropping chrominance data by going to 4:2:2 may reduce hardware area cost and power usage in the vertical scaler. Vertical filtering may be applied separately to luma and chroma to vertically downsize the YCC data. Chroma may be filtered with stronger filters than luma. The chroma 4:2:2 data may then be horizontally interpolated to generate chroma 4:4:4 data. The YCC data is converted back to RGB, and the RGB data is remosaiced to generate downsampled sensor format data.
Abstract translation: 用于图像信号处理器（ISP）的输入重定标模块，其在水平和垂直尺寸上降低传感器数据。 该模块可以将传感器数据拆分以产生RGB数据。 可以应用水平滤波来水平缩小RGB数据的尺寸。 RGB数据转换为YCC，色度4：4：4。 然后将色度4：4：4水平过滤以产生色度4：2：2。 通过转到4：2：2来降低色度数据可能会降低垂直缩放器中的硬件面积成本和功耗。 垂直滤波可以单独应用于亮度和色度，以垂直缩小YCC数据的大小。 色度可以用比亮度更强的滤光片过滤。 然后可以水平插入色度4：2：2数据以产生色度4：4：4数据。 YCC数据被转换回RGB，并且RGB数据被重新映射以产生下采样的传感器格式数据。
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7.发明授权公开(公告)号：US09131196B2
公开(公告)日：2015-09-08
申请号：US13724574
申请日：2012-12-21
Applicant: Apple Inc.
Inventor： Suk Hwan Lim , Christopher L. Mills , Sheng Lin
CPC classification number: H04N9/64 , H04N5/142 , H04N5/23229 , H04N5/23254 , H04N5/365 , H04N5/367 , H04N9/045 , H04N9/735
Abstract: The present disclosure generally relates to systems and methods for image data processing. In certain embodiments, an image processing pipeline may detect and correct a defective pixel of image data acquired using an image sensor. The image processing pipeline may receive an input pixel of the image data acquired using the image sensor. The image processing pipeline may then identify a set of neighboring pixels having the same color component as the input pixel and remove two neighboring pixels from the set of neighboring pixels thereby generating a modified set of neighboring pixels. Here, the two neighboring pixels correspond to a maximum pixel value and a minimum pixel value of the set of neighboring pixels. The image processing pipeline may then determine a gradient for each neighboring pixel in the modified set of neighboring pixels and determine whether the input pixel includes a dynamic defect or a speckle based at least in part on the gradient for each neighboring pixel in the modified set of neighboring pixels.
Abstract translation: 本公开通常涉及用于图像数据处理的系统和方法。 在某些实施例中，图像处理流水线可以检测和校正使用图像传感器获取的图像数据的缺陷像素。 图像处理流水线可以接收使用图像传感器获取的图像数据的输入像素。 然后，图像处理流水线可以识别具有与输入像素相同颜色分量的一组相邻像素，并从相邻像素组中移除两个相邻像素，从而生成修改后的相邻像素集合。 这里，两个相邻像素对应于该组相邻像素的最大像素值和最小像素值。 然后，图像处理流水线可以确定相邻像素的修改集合中的每个相邻像素的梯度，并且确定输入像素是否至少部分地基于修改的集合中的每个相邻像素的梯度的动态缺陷或散斑 相邻像素。
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公开(公告)号：US12229657B2
公开(公告)日：2025-02-18
申请号：US16596439
申请日：2019-10-08
Applicant: Apple Inc.
Inventor： Christopher L. Mills , Kenneth W. Waters , Youchang Kim
Abstract: Embodiments relate to a neural processor that include a plurality of neural engine circuits and one or more planar engine circuits. The plurality of neural engine circuits can perform convolution operations of input data of the neural engine circuits with one or more kernels to generate outputs. The planar engine circuit is coupled to the plurality of neural engine circuits. The planar engine circuit generates an output from input data that corresponds to output of the neural engine circuits or a version of input data of the neural processor. The planar engine circuit can be configured to multiple modes. In a pooling mode, the planar engine circuit reduces a spatial size of a version of the input data. In an elementwise mode, the planar engine circuit performs an elementwise operation on the input data. In a reduction mode, the planar engine circuit reduces the rank of a tensor.
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公开(公告)号：US12106206B2
公开(公告)日：2024-10-01
申请号：US17148432
申请日：2021-01-13
Applicant: Apple Inc.
Inventor： Christopher L. Mills , Sung Hee Park
CPC classification number: G06N3/063 , G06F7/24 , G06F7/50 , G06F7/523 , G06F7/5443
Abstract: Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.
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公开(公告)号：US20240265233A1
公开(公告)日：2024-08-08
申请号：US18614256
申请日：2024-03-22
Applicant: Apple Inc.
Inventor： Erik Norden , Liran Fishel , Sung Hee Park , Jaewon Shin , Christopher L. Mills , Seungjin Lee , Fernando A. Mujica
IPC: G06N3/04 , G06F1/3296 , G06N3/08
CPC classification number: G06N3/04 , G06F1/3296 , G06N3/08
Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.
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